Brady L Keays

6603682, Aug 5, 2003

Nov 18, 2002

10/298743

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518533, 36518529, 36523003, 36518905, 36523006, 36523008, 36518511

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6614695, Sep 2, 2003

Aug 24, 2001

09/939394

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518533, 36518529, 365218, 36518905, 36523003, 36523008, 365236

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6618293, Sep 9, 2003

Nov 18, 2002

10/298745

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518529, 36518533, 36518523, 36523006, 36523008, 365236

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6618294, Sep 9, 2003

Nov 18, 2002

10/298748

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518533, 36518529, 36518511, 36518519, 36518523, 36518525

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6646926, Nov 11, 2003

Nov 18, 2002

10/298763

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518529, 36518533, 36518519, 36518523, 36518524, 36518525, 36518905, 365218, 36523006, 36523008, 365236

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6646927, Nov 11, 2003

Nov 18, 2002

10/298839

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518533, 36518529, 36518519, 36518521, 36518523, 36518518, 36518511, 36518508, 36518505, 36518525, 36523003, 36523006, 36523008, 365236

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6650571, Nov 18, 2003

Nov 18, 2002

10/298777

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518533, 36518511, 36518519, 36518523, 36518524, 36518525, 36518529, 3651853, 365236, 36523008

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

6654292, Nov 25, 2003

Nov 18, 2002

10/298737

Brady L. Keays - Half Moon Bay CA

Micron Technology, Inc. - Boise ID

G11C 1604

36518533, 36518529, 3651853, 36518525, 36518523, 36518519, 36518511, 36518508, 36518904, 365218, 36523003, 36523008, 365236, 3652385

A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.