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Bradley Alan Orner

from Ben Lomond, CA
Age ~57
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Also known as:
Bradley A Orner
Related to:
Cindy Orner
Connected to:
Edward M Orner, 60Jacqueline A Orner, 60Jamie Orner, 48Laurie F Orner, 69Mark A Orner, 61Robyn Orner, 57Simon M Orner, 40Beverley L Ornes, 75Ashlynn J Orng, 43Sandra H Orni, 52

Bradley Orner Phones & Addresses

  • Ben Lomond, CA
  • 16 Duste Trl, Cambridge, VT 05444 (802) 849-9928
  • 72 Lost Nation Rd, Essex Jct, VT 05452
  • Essex Junction, VT
  • 47 Harbor Rd, Colchester, VT 05446 (802) 893-6050
  • 539 Harbor Rd, Colchester, VT 05446 (802) 893-6050
  • Fairfax, VT
  • Newark, DE
  • Florence, OR
  • South Burlington, VT
  • 16 Duste Trl, Cambridge, VT 05444

Work

Position: Craftsman/Blue Collar

Education

Degree: High school graduate or higher

Resumes

Resumes

Bradley Orner Photo 1

Senior Engineer At Ibm

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Location:
15 Polk Ct, North Potomac, MD 20878
Industry:
Information Technology And Services
Work:
Ibm
Senior Engineer at Ibm
Bradley Orner Photo 2

Bradley Orner

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Publications

Us Patents

Non-Continuous Encapsulation Layer For Mim Capacitor

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US Patent:
6913965, Jul 5, 2005
Filed:
Apr 15, 2004
Appl. No.:
10/709133
Inventors:
Wagdi W. Abadeer - Jericho VT, US
Eric Adler - Jericho VT, US
Zhong-Xiang He - Essex Junction VT, US
Bradley Orner - Colchester VT, US
Vidhya Ramachandran - Colchester VT, US
Barbara A. Waterhouse - Richmond VT, US
Michael Zierak - Essex Junction VT, US
Assignee:
International Busniess Machines Corporation - Armonk NY
International Classification:
H01L021/8242
US Classification:
438239, 438238, 438386, 438399, 438250, 438393, 257532, 257535, 257296, 257300
Abstract:
The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Non-Continuous Encapsulation Layer For Mim Capacitor

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US Patent:
7326987, Feb 5, 2008
Filed:
May 13, 2005
Appl. No.:
10/908491
Inventors:
Wagdi Abadeer - Jericho VT, US
Eric Adler - Jericho VT, US
Zhong-Xiang He - Essex Junction VT, US
Bradley Orner - Colchester VT, US
Vidhya Ramachandran - Colchester VT, US
Barbara A. Waterhouse - Richmond VT, US
Michael Zierak - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27/108
US Classification:
257306, 257532, 257638, 257E27048, 257E27071, 257E23144
Abstract:
The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Lateral Silicided Diodes

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US Patent:
7335927, Feb 26, 2008
Filed:
Jan 30, 2006
Appl. No.:
11/275794
Inventors:
Douglas Duane Coolbaugh - Essex Junction VT, US
Jeffrey Bowman Johnson - Essex Junction VT, US
Xuefeng Liu - South Burlington VT, US
Bradley Alan Orner - Fairfax VT, US
Robert Mark Rassel - Colchester VT, US
David Charles Sheridan - Williston VT, US
Assignee:
Internatioanl Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
257104, 257577, 257624, 257E27016, 257E27013, 257E27051, 257E27073, 257E29329, 257E21053, 257E21358, 257E21366, 438237
Abstract:
A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Lateral Silicided Diodes

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US Patent:
7381997, Jun 3, 2008
Filed:
Nov 26, 2007
Appl. No.:
11/944839
Inventors:
Douglas Duane Coolbaugh - Essex Junction VT, US
Jeffrey Bowman Johnson - Essex Junction VT, US
Xuefeng Liu - South Burlington VT, US
Bradley Alan Orner - Fairfax VT, US
Robert Mark Rassel - Colchester VT, US
David Charles Sheridan - Williston VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/329
US Classification:
257104, 257577, 257624, 257E27016, 257E27013, 257E27051, 257E27073, 257E29329, 257E21503, 257E21358, 257E21366, 438237
Abstract:
A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Varied Impurity Profile Region Formation For Varying Breakdown Voltage Of Devices

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US Patent:
7550787, Jun 23, 2009
Filed:
May 31, 2005
Appl. No.:
10/908884
Inventors:
Douglas D. Coolbaugh - Essex Junction VT, US
Louis D. Lanzerotti - Charlotte VT, US
Bradley A. Orner - Fairfax VT, US
Jay S. Rascoe - Underhill VT, US
David C. Sheridan - Williston VT, US
Stephen A. St. Onge - Colchester VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/737
US Classification:
257197, 257565, 257E29174
Abstract:
Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i. e. , the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

Method Of Base Formation In A Bicmos Process

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US Patent:
7625792, Dec 1, 2009
Filed:
Apr 6, 2005
Appl. No.:
10/599938
Inventors:
Peter J. Geiss - Underhill VT, US
Alvin J. Joseph - Williston VT, US
Qizhi Liu - Essex Junction VT, US
Bradley A. Orner - Colchester VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
438202, 438234, 257E21382
Abstract:
Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Deep Trench Based Far Subcollector Reachthrough

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US Patent:
7691734, Apr 6, 2010
Filed:
Mar 1, 2007
Appl. No.:
11/680637
Inventors:
Bradley A. Orner - Fairfax VT, US
Robert M. Rassel - Colchester VT, US
David C. Sheridan - Starkville MS, US
Steven H. Voldman - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/04
US Classification:
438510, 438 76, 438146, 438175, 438262, 438282, 438370, 438766, 438526, 257216, 257349, 257219, 257E21339, 257E21537, 257E21563, 257E2163, 257E2927
Abstract:
A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Bipolar And Cmos Integration With Reduced Contact Height

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US Patent:
7701015, Apr 20, 2010
Filed:
Dec 16, 2003
Appl. No.:
10/596573
Inventors:
Zhong-Xiang He - Essex Junction VT, US
Bradley A. Orner - Cambridge VT, US
Vidhya Ramachandran - Ossining NY, US
Alvin J. Joseph - Williston VT, US
Stephen A. St. Onge - Colchester VT, US
Ping-Chuan Wang - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/72
US Classification:
257370, 257378, 257E27109
Abstract:
Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
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Bradley Alan Orner from Ben Lomond, CA, age ~57 Get Report