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Bodhisattva Das

from Santa Clara, CA
Age ~53
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Also known as:
Boghisattva Das
Phone and address:
2318 Lass Dr, Santa Clara, CA 95054
(408) 654-9511
Connected to:
Abhaya K Das, 55Abhinab Das, 39Abreez K Das, 46Adhir R Das, 66Alak Das, 65Aloke K Das, 84Amarendra Das, 41Amber Das, 34Amlan K Das, 36Amulya Das, 90

Bodhisattva Das Phones & Addresses

  • 2318 Lass Dr, Santa Clara, CA 95054 (408) 654-9511
  • 104 University Blvd, Ames, IA 50010 (515) 292-5561
  • 870 Saratoga Ave, San Jose, CA 95129
  • 104 University Vlg UNIT D, Ames, IA 50010 (515) 238-7179

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Publications

Us Patents

Non-Volatile Spin Dependent Tunnel Junction Circuit

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US Patent:
6343032, Jan 29, 2002
Filed:
Jul 6, 2000
Appl. No.:
09/610503
Inventors:
William C. Black - Ames IA
Bodhisattva Das - Ames IA
Marwan M. Hassoun - Austin TX
Assignee:
Iowa State University Research Foundation, Inc. - Ames IA
International Classification:
G11C 1100
US Classification:
365158, 365 50, 365171, 365173, 365157
Abstract:
A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the âSenseâ cycles, the inputs to the latch cell are from spin dependent tunneling effect devices, each located in its respective inverter pair. The SDT magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained.

Nonvolatile Programmable Logic Devices

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US Patent:
6542000, Apr 1, 2003
Filed:
Jul 28, 2000
Appl. No.:
09/627576
Inventors:
William C. Black - Ames IA
Bodhisattva Das - Ames IA
Marwan M. Hassoun - Austin TX
Edward K. F. Lee - Austin TX
Assignee:
Iowa State University Research Foundation, Inc. - Ames IA
International Classification:
H03K 738
US Classification:
326 39, 326 40
Abstract:
In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2 GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.

Communication Signal Testing With A Programmable Logic Device

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US Patent:
7188283, Mar 6, 2007
Filed:
Sep 11, 2003
Appl. No.:
10/660243
Inventors:
Matthew S. Shafer - Ankeny IA, US
Bodhisattva Das - Ames IA, US
William C. Black - Ames IA, US
Scott A. Irwin - Ames IA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/28
G06F 11/00
US Classification:
714725, 714 3
Abstract:
Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Communication Signal Testing With A Programmable Logic Device

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US Patent:
7546499, Jun 9, 2009
Filed:
Jan 29, 2007
Appl. No.:
11/699113
Inventors:
Matthew S. Shafer - Ankeny IA, US
Bodhisattva Das - Ames IA, US
William C. Black - Ames IA, US
Scott Alan Irwin - Ames IA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G01R 31/28
US Classification:
714725, 714738
Abstract:
Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.
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Bodhisattva Das from Santa Clara, CA, age ~53 Get Report