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Bin Yang

from Owensboro, KY
Age ~59
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Also known as:
Yang Bin
Phone and address:
2403 Winning Colors Way, Owensboro, KY 42301
Related to:
Fengxian Kiang, 92Allen Yang, 30Wei Y Zhen, 50Wu Jian Bin, 55Jian K Wu, 47Jianming Ming Yang, 58Jia J Yang, 32Hong Yang, 36Jian K WuDa Q Ni, 64Jian Y Wu, 50Jiung J Yang, 34Jin H Wu, 81
Connected to:
Abby Yang, 32Addison Yang, 43Aileen C Yang, 51Alexandria L Yang, 33Allerina Yang, 33Alyssa J Yang, 36Amee Yang, 31Amy Yang, 57Andrew Yang, 34Anna Yang, 40

Bin Yang Phones & Addresses

  • 2403 Winning Colors Way, Owensboro, KY 42301
  • 2419 Haviland Dr, Owensboro, KY 42301
  • New York, NY
  • Fort Lee, NJ

Languages

English

Specialities

Occupational Medicine

Professional Records

License Records

Bin Yang

License #:
1206017552
Category:
Nail Technician License

Medicine Doctors

Bin Yang Photo 1

Dr. Bin Yang, East Orange NJ - MD (Doctor of Medicine)

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Specialties:
Occupational Medicine
Address:
385 Tremont Ave, East Orange, NJ 07018
(973) 676-1000 (Phone)
Languages:
English
Bin Yang Photo 2

Bin B. Yang

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Specialties:
Anatomic Pathology
Work:
Cleveland ClinicCleveland Clinic Pathology
9500 Euclid Ave, Cleveland, OH 44195
(216) 444-6781 (phone), (216) 445-6967 (fax)
Education:
Medical School
Henan Med Univ, Zhengzhou City, Henan, China
Graduated: 1982
Languages:
English
Description:
Dr. Yang graduated from the Henan Med Univ, Zhengzhou City, Henan, China in 1982. He works in Cleveland, OH and specializes in Anatomic Pathology. Dr. Yang is affiliated with Cleveland Clinic.
Bin Yang Photo 3

Bin Yang M.P.H.

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Specialties:
Occupational Medicine
Education:
Long Island University

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bin Yang
Occupational Therapy Director
Veterans Bio-Medical Research Institute, Inc
Business Services
385 Tremont Ave, East Orange, NJ 07018
(973) 676-1000
Bin Yang
BINARY METALS, LLC
Bin Yang
Principal
Y & Y Group of New York Inc
Business Consulting Services · Nonclassifiable Establishments
2055 W 4 St, Brooklyn, NY 11223
Bin Yang
Director, President, Secretary, Treasurer
Maxway Capital Group, Inc

Publications

Us Patents

Iii-V Power Field Effect Transistors

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US Patent:
7180103, Feb 20, 2007
Filed:
Sep 24, 2004
Appl. No.:
10/948897
Inventors:
Jeff D. Bude - New Providence NJ, US
Peide Ye - High Bridge NJ, US
Kwok K. Ng - Warren NJ, US
Bin Yang - Bridgewater NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 29/739
H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 31/109
US Classification:
257200, 257 11, 257189, 257201
Abstract:
A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

Method For Forming A Protection Layer Over Metal Semiconductor Contact And Structure Formed Thereon

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US Patent:
8030154, Oct 4, 2011
Filed:
Aug 3, 2010
Appl. No.:
12/849223
Inventors:
Ahmet S. Ozcan - Pleasantville NY, US
Christian Lavoie - Ossining NY, US
Zhen Zhang - Ossining NY, US
Bin Yang - Ossining NY, US
Assignee:
International Business Machines Corporation - Armonk NY
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 21/8238
US Classification:
438230, 438199, 438581, 438696
Abstract:
In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.

Method For Forming An Soi Schottky Source/Drain Device To Control Encroachment And Delamination Of Silicide

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US Patent:
8168503, May 1, 2012
Filed:
Mar 18, 2010
Appl. No.:
12/726736
Inventors:
Marwan H. Khater - Astoria NY, US
Christian Lavoie - Ossining NY, US
Bin Yang - Ossining NY, US
Zhen Zhang - Ossining NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/336
US Classification:
438300, 438285
Abstract:
A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10. 0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer.

Nmos Architecture Involving Epitaxially-Grown In-Situ N-Type-Doped Embedded Esige:c Source/Drain Targeting

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US Patent:
8178414, May 15, 2012
Filed:
Dec 7, 2009
Appl. No.:
12/632351
Inventors:
Bin Yang - Mahwah NJ, US
Bo Bai - Fishkill NY, US
Assignee:
Globalfoundries Inc. - Grand Cayman
International Classification:
H01L 21/02
US Classification:
438300, 438302, 438305, 438486, 438664, 257E21131, 257E21409, 257E21431, 257E21619, 257E29255
Abstract:
An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

Metal-Semiconductor Intermixed Regions

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US Patent:
8278200, Oct 2, 2012
Filed:
Jan 24, 2011
Appl. No.:
13/012043
Inventors:
Christian Lavoie - Pleasantville NY, US
Tak H. Ning - Yorktown Heights NY, US
Ahmet S. Ozcan - Pleasantville NY, US
Bin Yang - Ossining NY, US
Zhen Zhang - Ossining NY, US
Assignee:
International Business Machines Corpration - Armonk NY
Globalfoudries Inc. - Grand Cayman
International Classification:
H01L 21/20
US Classification:
438584, 438597, 438660, 438664, 257E21091, 427 69, 427 78
Abstract:
In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

Semiconductor Transistor Device Structure With Back Side Gate Contact Plugs, And Related Manufacturing Method

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US Patent:
8294211, Oct 23, 2012
Filed:
Jan 14, 2010
Appl. No.:
12/687610
Inventors:
Bin Yang - Mahwah NJ, US
Rohit Pal - Clifton Park NY, US
Michael Hargrove - Clinton Corners NY, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 29/786
US Classification:
257347, 257E21704, 257E27112, 257E29275, 438151
Abstract:
A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Efuse Enablement With Thin Polysilicon Or Amorphous-Silicon Gate-Stack For Hkmg Cmos

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US Patent:
8329515, Dec 11, 2012
Filed:
Dec 28, 2009
Appl. No.:
12/647888
Inventors:
Bin Yang - Mahwah NJ, US
Man Fai Ng - Poughkeepsie NY, US
Assignee:
Globalfoundries Inc. - Grand Cayman
International Classification:
H01L 21/82
US Classification:
438132, 257350
Abstract:
An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.

Semiconductor Transistor Device Structure With Back Side Source/Drain Contact Plugs, And Related Manufacturing Method

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US Patent:
8373228, Feb 12, 2013
Filed:
Jan 14, 2010
Appl. No.:
12/687607
Inventors:
Bin Yang - Mahwah NJ, US
Rohit Pal - Mahwah NJ, US
Michael Hargrove - Clinton Corners NJ, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 27/12
US Classification:
257347, 257E29275, 257E27112, 257E21704, 438666
Abstract:
A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

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Bin Yang

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Bin Yang from Owensboro, KY, age ~59 Get Report