Yowjuang B Liu

6344393, Feb 5, 2002

Jul 20, 2000

09/620339

Yowjuang W. Liu - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438259, 438262, 438266, 257315

A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench. The buried source region and the buried drain region have a depth slightly less than the depth of the trench.

6373103, Apr 16, 2002

Mar 31, 2000

09/541124

Wei Long - Sunnyvale CA
Qi Xiang - San Jose CA
Yowjuang W. Liu - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2701

257347, 257382

A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

6407558, Jun 18, 2002

Dec 15, 2000

09/738475

Sunil N. Shabde - Cupertino CA
Yowjuang William Liu - San Jose CA
Ting Yiu Tsui - Palo Alto CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 3126

324750, 250306, 324766

A method ( ) of determining a doping concentration of a semiconductor material ( ) includes the steps of moving carriers ( ) in the material, wherein a number of carriers is a function of the doping concentration of the material ( ). The carriers are deflected ( ) toward a surface ( ) of the material ( ) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected ( ) and used to calculate ( ) the doping concentration across a surface ( ) of the material ( ).

6441434, Aug 27, 2002

Mar 31, 2000

09/541126

Wei Long - Sunnyvale CA
Qi Xiang - San Jose CA
Yowjuang W. Liu - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2701

257347, 257349, 257382, 257384

A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

6461951, Oct 8, 2002

Mar 29, 1999

09/280662

Paul Besser - Sunnyvale CA
Angela Hui - Fremont CA
Yowjuang W. Liu - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 213205

438592, 438595, 438586, 438655, 257413

A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.

6525381, Feb 25, 2003

Mar 31, 2000

09/541127

Wei Long - Sunnyvale CA
Qi Xiang - San Jose CA
Yowjuang W. Liu - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2976

257384, 257347, 257349, 257382, 257383

A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

6528847, Mar 4, 2003

Jun 29, 1998

09/106178

Yowjuang William Liu - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2976

257330, 257331, 257332, 257333, 257334

A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (d ) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (d ), and contoured edges. The depth (d ) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (d ) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling. The effectively elongated channel length allows easier device optimization.

6667227, Dec 23, 2003

May 17, 2000

09/574695

Yowjuang W. Liu - San Jose CA
Donald L. Wollesen - Saratoga CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438589, 438197, 438270, 438282, 438585, 438592

A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.