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Bijit T Patel

from Allen, TX
Age ~59
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Also known as:
Bijit B Patel, Deepa Bijit Patel, Deepa B Patel, Biget T Patel, Beepa B Patel, Bijit Pattel, Patel T Bijit
Phone and address:
1034 Hot Springs Dr, Allen, TX 75013
(972) 678-0018
Related to:
Purujit J Patel, 61Raginiben Patel, 49Nipun Joshi, 45Hiten Patel, 42Yashodhara Patel, 71
Connected to:
A PatelAarzoo A Patel, 40Aashi R Patel, 25Aashil Patel, 43Aashish R Patel, 41Abbas A Patel, 62Abhinandan Patel, 62Aekta V Patel, 42Aimee Patel, 37Akib Patel, 29

Bijit Patel Phones & Addresses

  • 1034 Hot Springs Dr, Allen, TX 75013 (972) 678-0018
  • 205 Benton Dr, Allen, TX 75013 (972) 678-0018 (972) 678-0079 (972) 678-3424
  • 8009 Cross Creek Ct, Breinigsville, PA 18031 (610) 530-8608 (610) 560-8608
  • Emmaus, PA
  • Columbus, OH
  • Branchburg, NJ
  • South Burlington, VT
  • Colton, TX
  • Lehighton, PA
  • 1034 Hot Springs Dr, Allen, TX 75013

Work

Position: Sales Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Bijit Patel Photo 1

Senior Rfic Design Engineer, Mgts

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Senior Rfic Design Engineer, Mgts
Dongbu Hitek May 2009 - Mar 2011
Senior Rfic Design Engineer
Texas Instruments Aug 2006 - Apr 2009
Lead Rfic Design Engineer, Mgts
Pmc-Sierra Oct 1998 - Jul 2006
Leader Mixed-Signal Design
At&T Apr 1996 - Sep 1998
Member Technical Staff
Education:
The Ohio State University 1990 - 1992
Masters, Electrical Engineering The Ohio State University 1987 - 1990
Bachelors, Bachelor of Science, Electrical Engineering M. S. University
Gandhi Institute of Engineering and Technology (Giet), Gunupur
Bachelors
Skills:
Mixed Signal
Pll
Analog
Circuit Design
Asic
Soc
Serdes
Low Power Design
Analog Circuit Design
Electrical Engineering
Wireless
Bijit Patel Photo 2

Leader, Mixed-Signal

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Location:
1034 Hot Springs Dr, Allen, TX 75013
Industry:
Semiconductors
Work:
Pmc-Sierra
Leader, Mixed-Signal
Education:
The Ohio State University 1987 - 1992

Publications

Us Patents

Extended Frequency Range Voltage-Controlled Oscillator

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US Patent:
6621360, Sep 16, 2003
Filed:
Jan 22, 2002
Appl. No.:
10/056412
Inventors:
Chao Xu - Allentown PA
Bijit Thakorbhai Patel - Breinigsville PA
Assignee:
PMC-Sierra, Inc. - Santa Clara CA
International Classification:
H03B 2700
US Classification:
331 57, 331175, 327108
Abstract:
VCO frequency is continuously variable through a wide frequency range in proportion to a first control voltage VC produced by a PLL containing the VCO. A second control voltage NVC is produced as a monotonically decreasing function of VC. A first current I is produced in proportion to VC and a second current I is produced in proportion to NVC. I is subtracted from I , producing a control current IC=I -I which is applied to the VCO.

Multi-Function Bypass Port And Port Bypass Circuit

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US Patent:
7474612, Jan 6, 2009
Filed:
Mar 22, 2004
Appl. No.:
10/805441
Inventors:
Bijit T. Patel - Breinigsville PA, US
Assignee:
PMC- Sierra, Inc. - Santa Clara CA
International Classification:
H04J 1/16
H04J 3/06
US Classification:
370217, 370221, 370503
Abstract:
An architecture is provided for implementing bypass, repeater and retimer functions in high-speed multi-port SERDES bypass ports and devices. Specifically, this architecture uses clock recovery to implement a repeater function which retransmits data synchronously at a recovered-clock rate, providing very low-latency as no elastic-buffers are required to perform clock-rate compensation. It also supports a full retiming function where incoming data is retransmitted synchronously to the local-clock domain, in which case elastic-buffers are needed to compensate for differences between incoming clock and local-clock domains. The architecture disclosed herein is advantageously used for Fibre-Channel Arbitrated Loop (FCAL) applications. It can also be leveraged in other applications like Infiniband, XAUI, PCI-Express to create a single device that be used as “eye-opener” to extend reach with low-latency when operated in “repeater mode” and as retiming device when operated as “retimer-mode”. It can also perform as an amplifier with very low-latency when operated in bypass-mode.

Systems And Methods For Esd Protection

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US Patent:
7719806, May 18, 2010
Filed:
Feb 7, 2007
Appl. No.:
11/672304
Inventors:
Graeme B. Boyd - North Vancouver, CA
Xun Cheng - Chengdu, CN
Bijit Patel - Allen TX, US
Assignee:
PMC-Sierra, Inc. - Santa Clara CA
International Classification:
H02H 9/00
H02H 1/00
US Classification:
361 56
Abstract:
A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.

Multi-Mode Transceiver And A Circuit For Operating The Multi-Mode Transceiver

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US Patent:
20110171994, Jul 14, 2011
Filed:
Jan 8, 2010
Appl. No.:
12/684134
Inventors:
Gireesh RAJENDRAN - Trivandrum, IN
Timothy Don DAVIS - Arlington TX, US
Apu SIVADAS - Bangalore, IN
Michel FRECHETTE - Plano TX, US
Thiagarajan KRISHNASWAMY - Bangalore, IN
Salvatore PENNISI - Allen TX, US
Rakesh KUMAR - Ghazipur, IN
Bijit Thakorbhai PATEL - Allen TX, US
Subhashish MUKHERJEE - Bangalore, IN
Debapriya SAHU - Bangalore, IN
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04W 88/06
US Classification:
4555521
Abstract:
Multi-mode transceiver and a circuit for operating the multi-mode transceiver. A multi-mode transceiver includes a first circuit that is configurable to operate as one of a transmitter and a receiver in a first mode, and a second circuit that is configurable to operate as one of the transmitter and the receiver in a second mode. The multi-mode transceiver includes a first element coupled to the first circuit. The multi-mode transceiver includes a second element coupled to the first element and one or more ports. The multi-mode transceiver also includes a first switch, coupled to the second element and to the second circuit, that is configurable to operate the transceiver in at least one of the first mode and the second mode in conjunction with the first element and the second element.

Speed-Signaling Testing For Integrated Circuits

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US Patent:
60947357, Jul 25, 2000
Filed:
Aug 3, 1998
Appl. No.:
9/128041
Inventors:
Clifford B. Cole - Emmaus PA
Joseph D. Coyne - Lansdale PA
Bijit T. Patel - Breinigsville PA
Michael Shinkarovsky - Blue Bell PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G01R 3128
US Classification:
714724
Abstract:
An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.

Cmos High Voltage Drive Output Buffer

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US Patent:
60140399, Jan 11, 2000
Filed:
Apr 28, 1998
Appl. No.:
9/067936
Inventors:
Makeshwar Kothandaraman - Emmaus PA
Bernard Lee Morris - Emmaus PA
Bijit Thakorbhai Patel - Breinigsville PA
Wayne E. Werner - Coopersburg PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03K 190948
H03K 190185
US Classification:
326 83
Abstract:
A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e. g. , 5 V) during "hot pluggable" conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors are disposed around the output devices to provide the requisite protection. A backgate bias generator for use with P-channel devices is also disclosed that is capable of withstanding "hot pluggable" conditions.

High-Voltage-Tolerant Output Buffers In Low-Voltage Technology

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US Patent:
59330279, Aug 3, 1999
Filed:
Jun 19, 1997
Appl. No.:
8/879212
Inventors:
Bernard L. Morris - Emmaus PA
Bijit T. Patel - Breinigsville PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03K 190185
US Classification:
326 81
Abstract:
An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e. g. , PAD in FIG. 1) based on an input voltage (e. g. , A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.

Output Driver That Parks Output Before Going Tristate

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US Patent:
57845751, Jul 21, 1998
Filed:
Jul 24, 1996
Appl. No.:
8/685128
Inventors:
Steven F. Oakland - Colchester VT
Bijit T. Patel - Emmaus PA
Patrick E. Perry - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
395280
Abstract:
Disclosed is a tristate circuit driver capable of both parking the output in a deasserted state and switching to a tristate mode in less than one clock cycle. In a preferred embodiment, the driver circuitry utilized a delay device to generate a pulse signal immediately after the transition in an enable signal is detected. The pulse signal then causes the tristate driver to output a signal of a predetermined voltage for a duration of less then one clock cycle.
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Bijit T Patel from Allen, TX, age ~59 Get Report