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Bhushan Shanti Asuri

from San Diego, CA
Age ~49
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Also known as:
Bhushan Shant Asuri, Bhushan S Asuri, Asuri S Baushan, Asuri S Bhushan, Bhushan Shanti
Phone and address:
12843 Corbett Ct, San Diego, CA 92130
(949) 677-4939
Related to:
Geetanjali C Asuri, 47
Connected to:
Prashanth Asuri, 42Denisse Asurmendi, 52Renu Asuti, 34Thepphan Asvatanakul, 36Edward D Asvazadourian, 78Abdul S Aswad, 40Hanan J Aswad, 41Michael E Aswad, 62Muhammad Aswad, 71Stephanie A Aswad, 28

Bhushan Asuri Phones & Addresses

  • 12843 Corbett Ct, San Diego, CA 92130 (949) 677-4939
  • 14796 Carmel Ridge Rd, San Diego, CA 92128
  • Oak Park, CA
  • Los Angeles, CA
  • Irvine, CA
  • 45 Meadow View Dr, Pomona, CA 91766
  • Encino, CA

Resumes

Resumes

Bhushan Asuri Photo 1

Senior Director Of Technology

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Location:
12843 Corbett Ct, San Diego, CA 92130
Industry:
Telecommunications
Work:
Iqonic Corporation Jan 2005 - Dec 2006
Chief Executive Officer and Co-Founder
Qualcomm Jan 2005 - Dec 2006
Senior Director of Technology
Intel Corporation 2003 - 2006
Staff Engineer
Cognet Microsystems 2000 - 2003
Staff Engineer
Ucla 1996 - 2000
Research Assistant
Education:
University of California, Los Angeles 1996 - 2000
Doctorates, Doctor of Philosophy, Electronics Engineering, Philosophy Indian Institute of Technology, Bombay 1992 - 1996
Bachelors, Bachelor of Technology, Electrical Engineering, Electronics Engineering
Skills:
Semiconductors
Ic
Cmos
Radio Frequency
Analog Circuit Design
Languages:
English
Bhushan Asuri Photo 2

Bhushan Asuri

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Bhushan Asuri
Chief Executive Officer, CEO
Iqonic Corp
Mfg Electronics · Electronic Computers
14796 Carmel Rdg Rd, San Diego, CA 92128
(949) 677-4939

Publications

Us Patents

Laser Driver Circuit And System

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US Patent:
7142574, Nov 28, 2006
Filed:
May 21, 2003
Appl. No.:
10/442829
Inventors:
Bhushan S. Asuri - Oak Park CA, US
Ty Yoon - Calabasas CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01S 3/00
US Classification:
372 3802, 372 381
Abstract:
Described is a laser driver circuit to generate a bias current based, at least in part, upon a reference average power signal and a measured average power signal, and to generate a modulation current based, at least in part, upon a reference swing power and a measured swing power signal.

Filter With Signal Taps Temporally Spaced At Fractional Symbol Intervals

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US Patent:
7301998, Nov 27, 2007
Filed:
Dec 19, 2003
Appl. No.:
10/742119
Inventors:
Bhushan Asuri - Oak Park CA, US
Anush A. Krishnaswami - Los Angeles CA, US
William J. Chimitt - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5/159
US Classification:
375234, 375229, 375230
Abstract:
Described are methods and devices for processing a signal transmitting symbols which are temporally spaced on symbol intervals. The signal may be tapped at fractional symbol intervals to provide a plurality of signal taps at the fractional symbol intervals. Each of a plurality of coefficients may be applied to a corresponding one of the signal taps to generate an equalized signal. For at least one of the signal taps, the corresponding coefficient may be updated no more frequently than once per symbol interval.

Laser Driver Circuit And System

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US Patent:
7519093, Apr 14, 2009
Filed:
Aug 9, 2005
Appl. No.:
11/200368
Inventors:
Bhushan Asuri - Oak Park CA, US
Taesub Yoon - Calabasas CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01S 3/00
US Classification:
372 3802, 372 381, 372 3807
Abstract:
A method, system, and electrical circuit for determining a magnitude of a modulation current provided to a laser device based upon an approximated slope efficiency, wherein the approximated slope efficiency is based upon at least one discrete incremental change in a bias current to the laser device and at least one change in output power from the laser device.

Feedback Filter

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US Patent:
7561619, Jul 14, 2009
Filed:
Dec 19, 2003
Appl. No.:
10/741029
Inventors:
Bhushan Asuri - Oak Park CA, US
Anush A. Krishnaswami - Los Angeles CA, US
William J. Chimitt - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03H 7/30
US Classification:
375233, 375229, 375232, 375234, 379340, 379398, 381103, 708322, 708323
Abstract:
Disclosed are a system, method and device for generating an equalized signal from an input signal. Symbols in the equalized signal may be detected on each of a sequence of symbol intervals to recover a symbol value in the symbol interval. A feedback coefficient may be applied to a symbol value recovered in a previous symbol interval to generate the equalized signal in a current symbol interval. The feedback coefficient may be generated based, at least in part, on an estimated error associated with the equalized signal. The estimated error associated with the equalized output signal from among a plurality of candidate estimated error values.

Upconverter And Downconverter With Switched Transconductance And Lo Masking

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US Patent:
8095103, Jan 10, 2012
Filed:
Aug 1, 2008
Appl. No.:
12/185048
Inventors:
Bhushan Shanti Asuri - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H04B 15/00
H04B 1/26
US Classification:
455313, 455118, 455323
Abstract:
An upconverter and a downconverter having good performance are described. In one design, the upconverter includes first, second, and third sets of transistors. The first set of transistors receives baseband signals and provides an upconverted signal. The second set of transistors switches the transconductance of the transistors in the first set based on transmit (TX) local oscillator (LO) signals. The third set of transistors enables and disables the transistors in the second set based on a TX VCO signal. In one design, the downconverter includes first, second, and third sets of transistors. The first set of transistors receives a modulated signal and provides baseband signals. The second set of transistors switches the transconductance of the transistors in the first set based on receive (RX) LO signals. The third set of transistors enables and disables the transistors in the second set based on an RX VCO signal.

Configurable Digital-Analog Phase Locked Loop

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US Patent:
8339165, Dec 25, 2012
Filed:
Dec 7, 2009
Appl. No.:
12/632061
Inventors:
Jeremy D. Dunworth - San Diego CA, US
Gary J. Ballantyne - San Diego CA, US
Bhushan S. Asuri - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 7/00
US Classification:
327152, 327158, 327159, 375375, 375376
Abstract:
A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Phase Locked Loop With Digital Compensation For Analog Integration

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US Patent:
8446191, May 21, 2013
Filed:
Dec 7, 2009
Appl. No.:
12/632053
Inventors:
Jeremy D. Dunworth - San Diego CA, US
Gary J. Ballantyne - Christchurch, NZ
Bhushan S. Asuri - San Diego CA, US
Jifeng Geng - San Diego CA, US
Gurkanwal S. Sahota - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03L 7/06
US Classification:
327156, 327147
Abstract:
A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

Wideband Balun Having A Single Primary And Multiple Secondaries

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US Patent:
8493126, Jul 23, 2013
Filed:
Jul 15, 2010
Appl. No.:
12/836779
Inventors:
Janakiram G. Sankaranarayanan - San Diego CA, US
Bhushan S. Asuri - San Diego CA, US
Vinod V. Panikkath - San Diego CA, US
Hongyan Yan - San Diego CA, US
Himanshu Khatri - San Diego CA, US
Maulin Bhagat - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06G 7/12
US Classification:
327355, 455323, 327356
Abstract:
An RF transmitter capable of transmitting over a wide range of frequencies includes a mixer, a wideband high-Q balun, a first driver amplifier and a second driver amplifier. The balun has a single primary winding and two secondary windings. A differential output of the mixer is coupled to the primary winding. A first of the two secondary windings is coupled to drive the first driver amplifier. A second of the two secondary windings is coupled to drive the second driver amplifier. One driver amplifier is used when transmitting at lower frequencies whereas the other driver amplifier is used when transmitting at higher frequencies. By appropriate sizing of the inductances of the secondary windings and by switching out one of the secondary windings at certain times, the balun is tunable to operate over the wide frequency range while having a high quality factor Q, thereby facilitating reduced power consumption while simultaneously meeting performance requirements.
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Bhushan Shanti Asuri from San Diego, CA, age ~49 Get Report