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Bhaskar Bharath

from Durham, NC
Age ~45
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Also known as:
Bharath Bhasher, Bharath Bhaskar
Related to:
Viswa Bharath KollaBharathi Shankar Kannan, 34
Connected to:
Arun Bharath, 35Aruna T Bharati, 75Ashok S Bharathan, 58Desikan Bharathan, 76Robert A Bharath, 54Sandip Bharati, 44Aditi Bhardwaj, 46Alka Bhardwaj, 58Alok K Bhardwaj, 50Archna Bhardwaj, 51

Bhaskar Bharath Phones & Addresses

  • Durham, NC
  • 22 Village Brook Ln, Natick, MA 01760
  • Cary, NC
  • Austin, TX
  • Raleigh, NC

Resumes

Resumes

Bhaskar Bharath Photo 1

Staff Software Development Engineer

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Location:
Raleigh, NC
Industry:
Semiconductors
Work:
Triad Semiconductor
Staff Software Development Engineer
Viasic Jan 2004 - Jan 2011
Eda Development Engineer
Education:
North Carolina State University Jul 2001 - Dec 2003
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Madras Jul 1997 - May 2001
Bachelors, Bachelor of Technology, Electrical Engineering
Skills:
Asic
Eda
Static Timing Analysis
Fpga
Algorithms
Mixed Signal
Verilog
Semiconductors
Ic
System Architecture
Digital Electronics
Clock Tree Synthesis
Place and Route
Soc
Analog Circuit Design
Application Specific Integrated Circuits
Simulations
Field Programmable Gate Arrays
Electrical Engineering
Software Development
Cloud Computing
Integrated Circuits
R&D
Analog Design
Circuit Simulation
Timing Closure
Programmable Logic
System Level Design
C
C++
Python
Graph Theory
Optimization
Git
Javascript
Machine Learning
Data Structures
Python
C (Programming Language
Languages:
Hindi
Bhaskar Bharath Photo 2

Bhaskar Bharath

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Bhaskar Bharath Photo 3

Bhaskar Bharath

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Publications

Us Patents

Creating High-Drive Logic Devices From Standard Gates With Minimal Use Of Custom Masks

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US Patent:
7378874, May 27, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/469189
Inventors:
Bhaskar Bharath - Cary NC, US
William D. Cox - Chapel Hill NC, US
Assignee:
ViASIC, Inc. - Durham NC
International Classification:
H03K 19/173
US Classification:
326 47, 326 41, 326101, 716 12, 716 17
Abstract:
Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate equivalents in the standard cell architecture. The logic cells in the device may include, for example, at least two two-input multiplexers.
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Bhaskar Bharath from Durham, NC, age ~45 Get Report