Bernard J New

6346824, Feb 12, 2002

Jul 27, 2000

09/627247

Bernard J. New - Los Gatos CA

Xilinx, Inc. - San Jose CA

G06F 738

326 39, 326 40, 326 41

A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of dedicated function blocks. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of function blocks. However, selected CLEs can also be coupled to selected function blocks, thereby creating a relatively high density circuit to implement the dedicated function. The function blocks can be selectively coupled to one another, such that the function blocks are connected to form a relatively large circuit. The desired input signals are routed into the function blocks from associated CLEs. Similarly, the resulting output signals are routed from the function blocks to associated CLEs. In this manner, the FPGA is capable of implementing a relatively large circuit having the dedicated function in an efficient manner.

6362648, Mar 26, 2002

Nov 13, 2000

09/712038

Bernard J. New - Los Gatos CA
Steven P. Young - San Jose CA
Shekhar Bapat - Santa Clara CA
Kamal Chaudhary - San Jose CA
Trevor J. Bauer - San Jose CA
Roman Iwanczuk - Truckee CA

Xilinx, Inc. - San Jose CA

G06F 738

326 40, 326 41, 326 46

The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, â0â selecting the first AND signal and â1â selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.

6362650, Mar 26, 2002

May 18, 2000

09/574714

Bernard J. New - Los Gatos CA
Steven P. Young - San Jose CA

Xilinx, Inc. - San Jose CA

H03K 19177

326 41, 326 47

One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

6388466, May 14, 2002

Apr 27, 2001

09/844042

Ralph D. Wittig - Menlo Park CA
Sundararajarao Mohan - Sunnyvale CA
Bernard J. New - Los Gatos CA

Xilinx, Inc. - San Jose CA

H03K 19177

326 40, 326 41

A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby enabling the logic element to function as a lookup table by combining the outputs of the multiplexing circuits. However, each portion is also configurable as a shift register. The portions can function as separate shift registers, or can be concatenated to function as a single shift register. In some embodiments, the portions can also be concatenated with shift registers in other logic elements. Because two or more output multiplexing circuits are available, two or more taps are provided, one from each portion of the memory array.

6396302, May 28, 2002

May 18, 2001

09/860863

Bernard J. New - Los Gatos CA
Ralph D. Wittig - Menlo Park CA
Sundararajarao Mohan - Sunnyvale CA

Xilinx, Inc. - San Jose CA

G06F 738

326 38, 326 39, 326 41

A configurable logic element (CLE) for a field programmable gate array (FPGA) includes âexpandersâ, i. e. , connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

6400180, Jun 4, 2002

May 18, 2001

09/861261

Ralph D. Wittig - Menlo Park CA
Sundararajarao Mohan - Sunnyvale CA
Bernard J. New - Los Gatos CA

Xilinix, Inc. - San Jose CA

H01L 2500

326 41, 326 39, 326 38

A configurable logic element (CLE) for a field programmable gate array (FPGA) includes âexpandersâ, i. e. , connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

6492922, Dec 10, 2002

Dec 14, 2000

09/738005

Bernard J. New - Los Gatos CA

Xilinx Inc. - San Jose CA

H03M 110

341120, 341 61, 341155, 341144

An anti-aliasing filter with adaptable cutoff frequency. In various embodiments, the filter includes a calibrator/adaptor section and an anti-aliasing filter section. Both sections include a cascaded arrangement of adjustable delay circuits, and the calibrator/adaptor section includes a control circuit. A reference signal is input to the delay circuits and the control circuit of the calibrator/adaptor section, and an analog input signal is input to the delay circuits of the anti-aliasing filter. The control circuit compares the directly received reference signal to the reference signal from the last delay circuit and generate an adjustment signal responsive to the comparison. The delay intervals of all the delay circuits are adjustable responsive to the adjustment signal from the control circuit.

6573749, Jun 3, 2003

Jan 8, 2002

10/043958

Bernard J. New - Los Gatos CA
Steven P. Young - Boulder CO

Xilinx, Inc. - San Jose CA

H03K 19177

326 41, 326 39, 708232

One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.