Bernard B Gorowitz

55610854, Oct 1, 1996

Dec 19, 1994

8/359128

Bernard Gorowitz - Clifton Park NY
Charles A. Becker - Schenectady NY
Renato Guida - Wynantskill NY
Thomas B. Gorczyca - Schenectady NY
James W. Rose - Guilderland NY

Martin Marietta Corporation - King of Prussia PA

H01L 2160

437209

A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.

48248029, Apr 25, 1989

Oct 2, 1987

7/104002

Dale M. Brown - Schenectady NY
Bernard Gorowitz - Clifton Park NY
Richard J. Saia - Scotia NY

General Electric Company - Schenectady NY

H01L 21283
H01L 21312

437192

A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.

57364486, Apr 7, 1998

Dec 4, 1995

8/566616

Richard Joseph Saia - Schenectady NY
Kevin Matthew Durocher - Waterford NY
Bernard Gorowitz - Clifton Park NY

General Electric Company - Schenectady NY

H01L 2120

438393

A capacitor is fabricated on a base surface by applying a first pattern of electrical conductors (a first capacitor plate) over the base surface with an outer surface of the first pattern of electrical conductors including molybdenum. A first hard portion of a capacitor dielectric layer including amorphous hydrogenated carbon is deposited over the first capacitor plate and the base surface, a soft portion of the capacitor dielectric layer is deposited over the first hard portion, and a second hard portion of the capacitor dielectric layer is deposited over the soft portion. The deposition of the soft portion occurs at a lower bias voltage than the deposition of the first and second hard portions. A second pattern of electrical conductors (a second capacitor plate) is applied over the capacitor dielectric layer which is then patterned. A polymer layer is applied over the first and second capacitor plates, and two vias are formed, a first via extending to the first capacitor plate and a second via extending to the second capacitor plate.

55277411, Jun 18, 1996

Oct 11, 1994

8/321346

Herbert S. Cole - Burnt Hills NY
Raymond A. Fillion - Niskayuna NY
Bernard Gorowitz - Clifton Park NY
Ronald F. Kolc - Cherry Hill NJ
Robert J. Wojnarowski - Ballston Lake NY

Martin Marietta Corporation - Bethesda MD

H01L 2160

437209

A method for fabricating a circuit module includes applying an outer insulative layer over a first patterned metallization layer on a first surface of a base insulative layer. A second surface of the base insulative layer has a second patterned metallization layer. At least one circuit chip having chip pads is attached to the second surface of the base insulative layer. Respective vias are formed to expose selected portions of the first patterned metallization layer, the second patterned metallization layer, and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer to extend through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the first and second metallization layers.

45226814, Jun 11, 1985

Apr 23, 1984

6/602873

Bernard Gorowitz - Clifton Park NY
Richard J. Saia - Scotia NY

General Electric Company - Schenectady NY

B44C 122
C03C 1500
C03C 2506

156643

Holes in substrates are produced by a photolithography-plasma dry etching method employing a positive photoresist mask such as poly(methyl methacrylate) which is capable of being isotropically eroded by plasma action. The result is simultaneous anisotropic etching of the substrate and isotropic erosion of the mask, producing tapered holes.

40740064, Feb 14, 1978

Dec 16, 1976

5/751045

Edith M. Boldebuck - Schenectady NY
Bernard Gorowitz - Clifton Park NY

General Electric Company - Schenectady NY

C08G 6376

428379

Disclosed is a curable resinous coating composition which includes a polyester resin and a relatively small amount of a titanium-containing curing agent and optionally includes a surfactant and/or a powder free-flow agent. The composition is characterized with a suitable balance of cure rate and melt flow properties for powder coating and curing to form insulating films on magnet wire and other substrates.

53669061, Nov 22, 1994

Oct 16, 1992

7/962000

Robert J. Wojnarowski - Ballston Lake NY
Constantine A. Neugebauer - Schenectady NY
Wolfgang Daum - Schenectady NY
Bernard Gorowitz - Clifton Park NY
Eric J. Wildi - Niskayuna NY
Michael Gdula - Knox NY
Stanton E. Weaver - Northville NY
Anthony A. Immorlica - Manlius NY

Martin Marietta Corporation - Philadelphia PA

H01L 2166
G01R 3126

437 8

In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

56575378, Aug 19, 1997

May 30, 1995

8/453109

Richard Joseph Saia - Schenectady NY
Bernard Gorowitz - Clifton Park NY
Kevin Matthew Durocher - Waterford NY

General Electric Company - Schenectady NY

H05K 336

29830

A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates.