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Benjamin Wymore Phones & Addresses

  • Cortlandt Manor, NY
  • Mohegan Lake, NY
  • Lincoln, NE
  • Ossining, NY
  • Alexandria, MN
  • Fargo, ND

Work

Company: University of nebraska-lincoln Aug 2008 Position: Graduate research assistant

Education

School / High School: University of Nebraska-Lincoln- Lincoln, NE 2008 Specialities: PhD. in Chemistry, Electrochemistry, Physical Chemistry

Skills

Electrochemistry • Photolithography • E-beam Lithography • Thin Film sputtering • Thin Film Evaporation • Focus Ion Beam Milling • Scanning Electron Microscopy • Atomic Force Microscopy • Raman Spectroscopy • X-ray Diffraction • Reactive Ion Etching • Clean Room • Field Effect Transistor Measurements • Magnetoresistance Measurements • Ultraviolet-Visible Spectroscopy • Nuclear Magnetic Resonance.

Resumes

Resumes

Benjamin Wymore Photo 1

Benjamin Wymore Lincoln, NE

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Work:
University of Nebraska-Lincoln

Aug 2008 to 2000
Graduate Research Assistant

University of Nebraska-Lincoln
Lincoln, NE
Aug 2008 to Dec 2008
Teaching Assistant

North Dakota State University
Fargo, ND
Mar 2006 to Apr 2008
Undergraduate Research Assistant

Education:
University of Nebraska-Lincoln
Lincoln, NE
2008 to 2014
PhD. in Chemistry, Electrochemistry, Physical Chemistry

North Dakota State University
Fargo, ND
2004 to 2008
BS in Chemistry

Skills:
Electrochemistry, Photolithography, E-beam Lithography, Thin Film sputtering, Thin Film Evaporation, Focus Ion Beam Milling, Scanning Electron Microscopy, Atomic Force Microscopy, Raman Spectroscopy, X-ray Diffraction, Reactive Ion Etching, Clean Room, Field Effect Transistor Measurements, Magnetoresistance Measurements, Ultraviolet-Visible Spectroscopy, Nuclear Magnetic Resonance.

Publications

Us Patents

Junction Fabrication Method For Forming Qubits

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US Patent:
20210151660, May 20, 2021
Filed:
Nov 14, 2019
Appl. No.:
16/684423
Inventors:
- Armonk NY, US
Benjamin B. Wymore - Cortlandt Manor NY, US
Keith Fogel - Hopewell Junction NY, US
Martin O. Sandberg - Ossining NY, US
International Classification:
H01L 39/24
H01L 39/22
H01L 27/18
G06N 10/00
Abstract:
A method of making a Josephson junction for a superconducting qubit includes providing a substructure having a surface with first and second trenches perpendicular to each other defined therein. The method further includes evaporating a first superconducting material to deposit the first superconducting material and evaporating a second superconducting material to deposit the second superconducting material in the first trench to provide a first lead, and forming an oxidized layer on the first and second superconducting materials. The method includes evaporating a third superconducting material at an angle substantially perpendicular to the surface of the substructure to deposit the third superconducting material in the second trench without rotating the substructure to form a second lead. A vertical Josephson junction is formed at the intersection of the first and second trenches electrically connected through the first lead and through the second lead.

Polymer On Graphene

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US Patent:
20170141202, May 18, 2017
Filed:
Jan 30, 2017
Appl. No.:
15/419719
Inventors:
- Lincoln NE, US
Benjamin Wymore - Lincoln NE, US
International Classification:
H01L 29/51
H01L 29/66
H01L 21/04
H01L 29/16
H01L 29/786
Abstract:
A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.

Polymer On Graphene

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US Patent:
20150170906, Jun 18, 2015
Filed:
Nov 25, 2014
Appl. No.:
14/554000
Inventors:
- Lincoln NE, US
Benjamin Wymore - Lincoln NE, US
International Classification:
H01L 21/02
H01L 29/786
H01L 29/51
H01L 29/24
H01L 29/66
H01L 29/16
Abstract:
A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
Benjamin B Wymore from Cortlandt Manor, NY, age ~39 Get Report