Search

Belkacem Derras

from Longmont, CO
Age ~66
Get Report
Connected to:
Jean Derre, 55Kevin L Derreberry, 47Kamron O Derrell, 32Ashley K Derrenbacher, 39William D Derrenberger, 97Shawna Y Derrenkamp, 60Anna K Derrer, 42Gary V Derrera, 45Leah E Derrera, 44Sira Derrera, 36

Belkacem Derras Phones & Addresses

  • 620 Grandview Mdws Dr, Longmont, CO 80503 (303) 682-9287
  • 1009 9Th Ave, Broomfield, CO 80020 (303) 465-2133
  • 1009 E 9Th Ave #104, Broomfield, CO 80020 (303) 465-2133
  • 11087 Claude Ct, Northglenn, CO 80233 (303) 920-1048
  • Denver, CO
  • 1009 E 9Th Ave APT 104, Broomfield, CO 80020 (303) 514-3722

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Associate degree or higher

Emails

b***[email protected]

Resumes

Resumes

Belkacem Derras Photo 1

Belkacem Derras

View page
Location:
Greater Denver Area
Industry:
Computer Hardware
Skills:
Debugging
Failure Analysis
Firmware
SCSI
Belkacem Derras Photo 2

Belkacem Derras

View page

Publications

Us Patents

Viterbi Detector That Associates Multiple Data Dependent Noise Prediction Filters With Each Possible Bit Pattern

View page
US Patent:
8296638, Oct 23, 2012
Filed:
May 4, 2009
Appl. No.:
12/434958
Inventors:
Belkacem Derras - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H03M 13/03
US Classification:
714795, 714794, 714796, 375341, 360 46, 370242
Abstract:
A Viterbi detector includes a plurality of possible bit patterns that correspond to branches of a detector trellis and a plurality of data dependent noise prediction filters, with multiple filters of different orders being associated with a given bit pattern. A method of decoding includes applying observables to a Viterbi detector that associates a plurality of data dependent noise filters with a given possible bit pattern that corresponds to a branch of the detector trellis, calculating the composite maximum likelihood branch metric by incorporating the results of filtering the observables through the associated plurality of filters, calculating the composite maximum likelihood branch metrics in the same manner for other possible bit patterns, and so forth, and associating soft output values with detected bits in the observables based on the calculated branch metrics.

Self-Adapting Phase-Locked Loop Filter For Use In A Read Channel

View page
US Patent:
20170085364, Mar 23, 2017
Filed:
Dec 6, 2016
Appl. No.:
15/370960
Inventors:
- Cupertino CA, US
Belkacem Derras - Longmont CO, US
William Michael Radich - Longmont CO, US
Michael J. Link - St. Paul MN, US
Bruce D. Buch - Westborough MA, US
International Classification:
H04L 7/033
H04L 12/26
H04L 1/00
Abstract:
A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Phase Error Recovery Circuitry And Method For A Magnetic Recording Device

View page
US Patent:
20170025147, Jan 26, 2017
Filed:
Jul 24, 2015
Appl. No.:
14/808721
Inventors:
- Cupertino CA, US
Bruce Douglas Buch - Westborough MA, US
Belkacem Derras - Longmont CO, US
International Classification:
G11B 20/10
G11B 20/18
G11B 5/09
Abstract:
A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.
Control profile
Belkacem Derras from Longmont, CO, age ~66 Get Report