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Behnam E Moradi

from Haymarket, VA
Age ~66
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Also known as:
Behnam Morady, Bahram Moradi, Behrem Moradi, Behnam Moradi Balani, Moradi Benham
Phone and address:
15152 Golf View Dr, Haymarket, VA 20169
(703) 754-4178
Related to:
Tahereh F BalaniTahereh F Balani, 54Saeed F Ballani, 51Piam Moradi, 31
Connected to:
Abbas Moradian, 104Eli Moradi, 32Gail D Moradi, 79Ghasem Moradi, 87Hadi K Moradi, 72Jafar M Moradi, 70Michael M Moradi, 78Mohamad R Moradi, 76Morteza Moradi, 91Nasrin Moradi, 57

Behnam Moradi Phones & Addresses

  • 15152 Golf View Dr, Haymarket, VA 20169 (703) 754-4178
  • Reston, VA
  • Manassas, VA
  • 2460 Mariner Way, Boise, ID 83706 (208) 368-0975
  • Bristow, VA
  • Prince William, VA
  • Ames, IA
  • 2460 S Mariner Way #O-206O, Boise, ID 83706 (208) 368-0975

Work

Position: Sales Occupations

Education

Degree: High school graduate or higher

Publications

Us Patents

Field Emission Display Having Reduced Optical Sensitivity And Method

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US Patent:
6353285, Mar 5, 2002
Filed:
Jul 24, 2000
Appl. No.:
09/624362
Inventors:
John K. Lee - Meridian ID
Behnam Moradi - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01J 162
US Classification:
313495, 313309, 313336, 313351
Abstract:
An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid. This reduces distortion in field emission displays.

Extraction Grid For Field Emission Displays And Method

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US Patent:
6361392, Mar 26, 2002
Filed:
May 18, 2001
Appl. No.:
09/860256
Inventors:
Behnam Moradi - Boise ID
Tianhong Zhang - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01J 902
US Classification:
445 24
Abstract:
A display apparatus includes a substrate and a plurality of emitters formed on the substrate. The apparatus also includes a dielectric layer formed on the substrate. The dielectric layer includes a plurality of openings each formed about one of the plurality of emitters. The dielectric layer and extraction grid together have a thickness, measured perpendicular to the substrate, similar to a height of the emitters above the substrate. The apparatus also includes an extraction grid formed on the dielectric layer. The extraction grid is formed substantially in a plane of tips of the plurality of emitters and includes openings each formed about and in close proximity to a tip of one of the plurality of emitters. The extraction grid includes germanium so that photons incident on exposed portions of the extraction grid are absorbed and are not transmitted to depletion regions associated with the emitters. This reduces distortion in operation of the display.

Low And High Voltage Cmos Devices And Process For Fabricating Same

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US Patent:
6362038, Mar 26, 2002
Filed:
May 1, 2000
Appl. No.:
09/563039
Inventors:
John K. Lee - Meridian ID
Behnam Moradi - Boise ID
Michael J. Westphal - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 218238
US Classification:
438225, 438362
Abstract:
CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Titanium Silicide Nitride Emitters And Method

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US Patent:
6417617, Jul 9, 2002
Filed:
Jul 24, 2001
Appl. No.:
09/912618
Inventors:
Tianhong Zhang - Boise ID
John K. Lee - Boise ID
Behnam Moradi - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01J 130
US Classification:
313495, 313309, 313336, 313351, 313310, 313311
Abstract:
A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.

Field Emission Display Having Reduced Optical Sensitivity And Method

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US Patent:
6436788, Aug 20, 2002
Filed:
Jul 30, 1998
Appl. No.:
09/126695
Inventors:
John K. Lee - Meridian ID
Behnam Moradi - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2176
US Classification:
438414, 438 20, 438139, 313495, 313309
Abstract:
An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid. This reduces distortion in field emission displays.

Titanium Silicide Nitride Emitters And Method

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US Patent:
6471561, Oct 29, 2002
Filed:
Jul 25, 2001
Appl. No.:
09/916159
Inventors:
Tianhong Zhang - Boise ID
John K. Lee - Boise ID
Behnam Moradi - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01J 902
US Classification:
445 50, 445 58
Abstract:
A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.

Light-Insensitive Resistor For Current-Limiting Of Field Emission Displays

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US Patent:
6507329, Jan 14, 2003
Filed:
Jan 30, 2001
Appl. No.:
09/774812
Inventors:
Kevin W. Tjaden - Boise ID
Behnam Moradi - Boise ID
John K. Lee - Meridian ID
James J. Alwan - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G09G 322
US Classification:
345 752, 3151693
Abstract:
A semiconductor device for use in field emission displays includes a substrate formed from a semiconductor material, glass, soda lime, or plastic. A first layer of a conductive material is formed on the substrate. A second layer of microcrystalline silicon is formed on the first layer. This layer has characteristics that do not fluctuate in response to conditions that vary during the operation of the field emission display, particularly the varying light intensity from the emitted electrons or from the ambient. One or more cold-cathode emitters are formed on the second layer.

Field Emission Display Cathode Assembly With Gate Buffer Layer

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US Patent:
6509686, Jan 21, 2003
Filed:
Sep 16, 1999
Appl. No.:
09/398155
Inventors:
Behnam Moradi - Boise ID
Kanwal K. Raina - Boise ID
Michael J. Westphal - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01J 1304
US Classification:
313495, 313309, 313336, 313351
Abstract:
Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.
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Behnam E Moradi from Haymarket, VA, age ~66 Get Report