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Behnam Behnam Amelifard

from San Diego, CA
Age ~46
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Also known as:
Behnam Ameli, Ameli Behnam
Phone and address:
6310 Quail Run St, San Diego, CA 92130
Connected to:
Alfred J Ameling, 66Bradly R Ameling, 45Brent P Amelingmeier, 49Brooke Ameling, 32Keith D Ameling, 68Melissa M Ameline, 41Anthony T Amelio, 61Gayle M Amelio, 38Kathryn Amelio, 39Shawn M Amelio, 50

Behnam Amelifard Phones & Addresses

  • 6310 Quail Run St, San Diego, CA 92130
  • La Jolla, CA
  • Los Angeles, CA

Work

Company: Qualcomm 2008 Position: Senior staff design engineer

Education

Degree: Ph.D. School / High School: University of Southern California 2003 to 2007 Specialities: Electrical Engineering

Skills

Verilog • Vlsi • Digital Signal Processors • Integrated Circuit Design • Eda • Rtl Design • Algorithms • Computer Architecture • C++

Industries

Wireless

Resumes

Resumes

Behnam Amelifard Photo 1

Director Of Engineering

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Location:
San Diego, CA
Industry:
Wireless
Work:
Qualcomm since 2008
Senior Staff Design Engineer
Magma Design Automation May 2006 - Aug 2006
Member of R&D Staff
Fujitsu Labs. of America May 2005 - Aug 2005
Member of R&D Staff
Education:
University of Southern California 2003 - 2007
Ph.D., Electrical Engineering University of Tehran 2001 - 2003
M.Sc, Electrical Engineering Sharif University of Technology 1997 - 2001
B.Sc, Electrical Engineering
Skills:
Verilog
Vlsi
Digital Signal Processors
Integrated Circuit Design
Eda
Rtl Design
Algorithms
Computer Architecture
C++

Publications

Us Patents

Setting Threshold Voltages Of Cells In A Memory Block To Reduce Leakage In The Memory Block

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US Patent:
7573775, Aug 11, 2009
Filed:
Feb 9, 2007
Appl. No.:
11/673245
Inventors:
Farzan Fallah - San Jose CA, US
Behnam Amelifard - Los Angeles CA, US
Massoud Pedram - Beverly Hills CA, US
Assignee:
Fujitsu Limited - Kanagawa
International Classification:
G11C 5/14
US Classification:
365227, 365229, 365194, 365 51, 365 63, 365156, 365206, 36523006, 36523005
Abstract:
In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Pg-Gated Data Retention Technique For Reducing Leakage In Memory Cells

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US Patent:
20080151673, Jun 26, 2008
Filed:
Dec 22, 2006
Appl. No.:
11/615422
Inventors:
Farzan Fallah - San Jose CA, US
Behnam Amelifard - Los Angeles CA, US
Massoud Pedram - Beverly Hills CA, US
International Classification:
G11C 5/14
US Classification:
365226
Abstract:
A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

Adaptive Output Swing Driver

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US Patent:
20130120020, May 16, 2013
Filed:
Nov 11, 2011
Appl. No.:
13/294482
Inventors:
Miao Li - San Diego CA, US
Behnam Amelifard - San Diego CA, US
Xiaohua Kong - San Diego CA, US
Nam V. Dang - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H03K 19/003
US Classification:
326 30
Abstract:
An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.

Dual Mode Clock/Data Recovery Circuit

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US Patent:
20130191679, Jul 25, 2013
Filed:
Mar 15, 2012
Appl. No.:
13/420800
Inventors:
Jingcheng Zhuang - San Diego CA, US
Nam V. Dang - San Diego CA, US
Xiaohua Kong - San Diego CA, US
Zhi Zhu - San Diego CA, US
Tirdad Sowlati - Irvine CA, US
Behnam Amelifard - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 1/24
US Classification:
713503
Abstract:
A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Apparatuses, Methods, And Systems For Glitch-Free Clock Switching

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US Patent:
20160269034, Sep 15, 2016
Filed:
Mar 13, 2015
Appl. No.:
14/657225
Inventors:
- San Diego CA, US
Behnam Amelifard - San Diego CA, US
Kenneth Luis Arcudia - Cary NC, US
Jon Raymond Boyette - Holly Springs NC, US
Chia Heng Chang - San Diego CA, US
Russell Coleman Deans - Chapel Hill NC, US
Kevin Wayne Spears - Raleigh NC, US
International Classification:
H03L 7/08
G06F 1/12
Abstract:
Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

Continuous Analog Signal Monitoring

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US Patent:
20160065235, Mar 3, 2016
Filed:
Sep 3, 2014
Appl. No.:
14/476653
Inventors:
- San Diego CA, US
Thuan LY - San Diego CA, US
Behnam AMELIFARD - San Diego CA, US
Ohjoon KWON - Irvine CA, US
International Classification:
H03M 3/00
Abstract:
An integrated circuit includes a first circuit configured to convert a digital signal of a first format, which includes a sampled version of an analog signal, to a digital signal of a second format. A second circuit is configured to output the digital signal of the second format through a digital interface. An electronic system including a circuit configured to output a digital signal of the analog signal as a bitstream is provided. A clock generator generates a clock for clocking the bitstream. In another aspect, a method for operating an integrated circuit includes converting a digital signal of a first format, which includes a sampled version of an analog signal, to a digital signal of a second format. The digital signal of the second format is outputted through a digital interface. A monitoring or observing device receives directly the digital signal of the second format through the digital interface.
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Behnam Behnam Amelifard from San Diego, CA, age ~46 Get Report