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Baylor B Triplett

from Kealakekua, HI
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Also known as:
Baylor Baylor B Triplett, B Triplett, Triplett Baylor
Connected to:
Albert J Triplett, 64Alexa M Triplett, 35Amy G Triplet, 94Andre D Triplett, 59Angie Triplett, 49Bonzell R Triplett, 77Brandy J Triplet, 47Breacella Triplett, 43Brianna D Triplett, 35Bryce Triplett, 32

Baylor Triplett Phones & Addresses

  • Kealakekua, HI
  • 200 Portola State Park Rd, La Honda, CA 94020 (650) 948-3285
  • San Francisco, CA
  • 200 Portola State Park Rd, La Honda, CA 94020

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Baylor Triplett Photo 1

Adjunct Professor

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Work:

Adjunct Professor
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Baylor Triplett

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Publications

Us Patents

High-K Dielectric For Thermodynamically-Stable Substrate-Type Materials

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US Patent:
7271458, Sep 18, 2007
Filed:
Mar 31, 2003
Appl. No.:
10/404876
Inventors:
Chi On Chui - San Mateo CA, US
Krishna C. Saraswat - Saratoga CA, US
Baylor B. Triplett - La Honda CA, US
Paul McIntyre - Sunnyvale CA, US
Assignee:
The Board of Trustees of the LeLand Stanford Junior University - Palo Alto CA
International Classification:
H01L 29/76
US Classification:
257410, 257411
Abstract:
Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiOequivalent (“T”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.

Process For Removing A Liquid Phase Epitaxial Layer From A Wafer

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US Patent:
43728081, Feb 8, 1983
Filed:
Mar 22, 1982
Appl. No.:
6/360809
Inventors:
Baylor B. Triplett - La Honda CA
Carlo Ferrando - Aptos CA
Guido Galli - Saratoga CA
Assignee:
Intel Magnetics, Inc. - Santa Clara CA
International Classification:
H01L 21312
B44C 122
US Classification:
156655
Abstract:
A process for removing a liquid phase epitaxial layer of material from a wafer substrate is disclosed. An etch melt is provided which is substantially the same as that used to grow the epitaxial layer on the wafer surface. The temperature of the etch melt is adjusted such that it exceeds an equilibrium temperature of the epitaxial layer, and lies below an equilibrium temperature of the substrate, such that the epitaxial layer is etched away without affecting the substrate material. The wafer is immersed and maintained within the melt until the epitaxial layer is removed. The wafer may then be reused without repolishing.

Method Of Reducing Hot-Electron Degradation In Semiconductor Devices

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US Patent:
52293114, Jul 20, 1993
Filed:
Mar 25, 1992
Appl. No.:
7/859264
Inventors:
Stefan K. Lai - Belmont CA
Daniel N. Tang - San Jose CA
Simon Y. Wang - Sunnyvale CA
Susan L. Kao - Los Altos CA
Baylor B. Triplett - La Honda CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2170
US Classification:
437 43
Abstract:
A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed. The method of the present invention includes covering the active regions of the semiconductor device with a protective titanium barrier layer which is deposited directly underneath the ordinary metalization layers used for connecting the devices to bit and word lines within an array. Inclusion of the titanium barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices.
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Baylor B Triplett from Kealakekua, HI Get Report