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Bardia Zandian

from Redwood City, CA
Age ~43
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Also known as:
Zandian Barida
Related to:
Anthony Zandian, 44Wilfredo DesouzaRaymond Peart, 77Erica Desouza, 49Joel R Peart, 46Renee Mcguire, 44Jacqulyn R Peart, 40
Connected to:
Reza Zandieh, 53Shohreh S Zandieh, 72Michael A Zandier, 38Amir A Zandinejad, 54David J Zandlo, 84Richard G Zandlo, 54Linda A Zandona, 75Michael J Zandona, 47Lili Zandpour, 47Vincent A Zandri, 60

Bardia Zandian Phones & Addresses

  • Redwood City, CA
  • 3485 Monroe St APT 439, Santa Clara, CA 95051
  • San Diego, CA
  • Calabasas, CA
  • 550 Barrington Ave, Los Angeles, CA 90049 (310) 471-3841

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Southern California 2008 to 2012 Specialities: Philosophy

Industries

Computer Hardware

Resumes

Resumes

Bardia Zandian Photo 1

Bardia Zandian

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Location:
3485 Monroe St, Santa Clara, CA 95051
Industry:
Computer Hardware
Education:
University of Southern California 2008 - 2012
Doctorates, Doctor of Philosophy, Philosophy University of Southern California 2006 - 2008
Master of Science, Masters

Publications

Us Patents

Automated Detection Of And Compensation For Guardband Degradation During Operation Of Clocked Data Processing Circuit

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US Patent:
20120159276, Jun 21, 2012
Filed:
Dec 15, 2011
Appl. No.:
13/327561
Inventors:
Bardia ZANDIAN - Los Angeles CA, US
Murali ANNAVARAM - Los Angeles CA, US
Assignee:
UNIVERSITY OF SOUTHERN CALIFORNIA - Los Angeles CA
International Classification:
G01R 31/3181
US Classification:
714734
Abstract:
An automated guardband compensation system may automatically compensate for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit may automatically and repeatedly request: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.

Optimal Operating Point Estimator For Hardware Operating Under A Shared Power/Thermal Constraint

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US Patent:
20200142466, May 7, 2020
Filed:
Nov 2, 2018
Appl. No.:
16/179620
Inventors:
- Santa Clara CA, US
Siddharth Bhargav - Campbell CA, US
Bardia Zandian - Santa Clara CA, US
Narayan Kulshrestha - Fremont CA, US
Amit Pabalkar - Fremont CA, US
Arvind Gopalakrishnan - Fremont CA, US
Justin Tai - San Jose CA, US
Sachin Satish Idgunji - San Jose CA, US
International Classification:
G06F 1/32
G06F 9/50
G06F 1/28
G06N 99/00
Abstract:
Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.
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Bardia Zandian from Redwood City, CA, age ~43 Get Report