Bandan S Das

20210240644, Aug 5, 2021

Jan 30, 2020

16/777366

- Raleigh NC, US
Bandan Das - Westford MA, US

G06F 13/24
G06F 9/455

According to one example, a method includes, with a hypervisor, advertising a paravirtualized cluster mode for a guest using a legacy Advanced Programmable Interrupt Controller (APIC), the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight. The method further includes, associating each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2different values. The method further includes, with the hypervisor, in response to receiving an interrupt for the virtual machine, determining to which of the plurality of virtual cores the interrupt should be sent based on at least a subset of bits in a destination address of the interrupt.

20210124601, Apr 29, 2021

Oct 23, 2019

16/661224

- Raleigh NC, US
Bandan Das - Westford MA, US

G06F 9/455

Implementing high-performance virtual machines for bare metal simulation is disclosed. A hypervisor executing on a host computer receives a request to initiate a high-performance (HP) virtual machine (VM). The hypervisor selects, based on the request, a HP virtual machine exit (VMEXIT) configuration from a plurality of different VMEXIT configurations. Each respective VMEXIT configuration of the plurality of different VMEXIT configurations identifies VMEXIT behavior in response to a task executing in a VM having a virtual machine control structure (VMCS) generated based on the respective VMEXIT configuration. The hypervisor generates a HP VMCS for the HP VM based on the HP VMEXIT configuration, the HP VMCS controlling the VMEXIT behavior in response to a task executing in the HP VM. The hypervisor initiates the HP VM.

20210096896, Apr 1, 2021

Sep 27, 2019

16/585067

- Raleigh NC, US
Bandan Das - Westford MA, US

G06F 9/455
G06F 9/50
G06F 9/48
G06F 1/28

Processor core power management in a virtualized environment. A hypervisor, executing on a processor device of a computing host, the processor device having a plurality of processor cores, receives from a guest operating system of a virtual machine, a request to set a virtual central processing unit (VCPU) of the virtual machine to a first requested P-state level of a plurality of P-state levels. Based on the request, the hypervisor associates the VCPU with a first processor core having a P-state that corresponds to the first requested P-state level.

20210064252, Mar 4, 2021

Aug 27, 2019

16/552007

- Raleigh NC, US
Bandan Das - Westford MA, US

G06F 3/06
G06F 9/455

Inhibiting memory accesses to executable modules. A hypervisor executing on a computing host initiates a virtual machine comprising a guest operating system. The hypervisor receives a communication from the guest operating system requesting that a range of memory utilized by the guest operating system be identified as being execute-only access. The hypervisor marks at least one physical page of memory that includes the range of memory as being execute-only access.

20200326962, Oct 15, 2020

Apr 10, 2019

16/379868

- Raleigh NC, US
Bandan Das - Westford MA, US

G06F 9/455
G06F 13/42

A controller sandbox using an emulation framework of a hypervisor is disclosed. A hypervisor receives, from a task in a virtual machine that is controlled by the hypervisor in a computing device on which the hypervisor executes, a first implement device command request that requests that a first device command be implemented on a controllable device communicatively connected to the computing device via an interface. The hypervisor determines that the first device command is on an authorized device command list. Based on determining that the first device command is on the authorized device command list, the hypervisor communicates a signal to the controllable device to implement the first device command.

20200201663, Jun 25, 2020

Dec 21, 2018

16/229897

- Raleigh NC, US
Bandan Das - Wakefield MA, US

G06F 9/455
G06F 9/50
G06F 9/48

Certain aspects and feature provide a host hypervisor that includes and advertises a virtual machine function that directs the host hypervisor to execute the next job with real-time priorities. A processing device can execute an application in a nested virtual machine, where the application includes at least one code section that relies on or makes use of real-time prioritized resources of the processing device. The processing device recognizes a virtual machine function call in response to the application determining that a code section using real-time prioritized resources is to be executed. The virtual machine function serves as a command that directs a host hypervisor to execute the next job (the next section of code to be executed) with real-time priorities. The processing device executes the code section in a real-time thread in response to the virtual machine function being called.

20190205259, Jul 4, 2019

Dec 29, 2017

15/858619

- Raleigh NC, US
Bandan Das - Westford MA, US

G06F 12/1009

A system and method of exitless extended page table switching includes a nested hypervisor writing pointer addresses to an extended page table list, where each pointer address is associated with an extended page table. The host hypervisor verifies that each pointer address corresponds to a guest physical address for one of the extended page tables. The host hypervisor then creates shadow extended page tables, each of which includes a shadow pointer address corresponding to a host physical address, writes, in a local page table list, each shadow pointer address and an index of each shadow extended page table, and loads the local page table list. The nested guest requests to switch between two extended page tables. The nested guest then identifies a matching entry for an extended page table in the local page table list and switches to the extended page table without triggering an exit.

20180365163, Dec 20, 2018

Jun 20, 2017

15/628079

- Raleigh NC, US
Bandan Souryakanta Das - Wakefield MA, US

G06F 12/1027
G06F 9/30
G06F 9/455

Methods, systems, and computer program products are included for switching from a first guest virtual address (GVA)-to-host physical address (HPA) translation mode to a second GVA-to-HPA translation mode. A method includes comparing, by a hypervisor, a number of translation lookaside buffer (TLB) misses to a miss threshold, the hypervisor being in a first GVA-to-HPA translation mode. The method includes switching from the first GVA-to-HPA translation mode to a second GVA-to-HPA translation mode if the number of TLB misses satisfies the miss threshold.