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Avinash Karanth Kodi

from Canal Winchester, OH
Age ~47

Avinash Kodi Phones & Addresses

  • 7521 Burgstresser Ct, Canal Wnchstr, OH 43110
  • Canal Winchester, OH
  • Athens, OH
  • Tucson, AZ
  • Franklin, OH
  • Canal Wnchstr, OH

Work

Company: Ohio university Sep 2007 Position: Assistant professor

Industries

Higher Education

Resumes

Resumes

Avinash Kodi Photo 1

Assistant Professor

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Location:
7521 Burgstresser Ct, Canal Winchester, OH 43110
Industry:
Higher Education
Work:
Ohio University
Assistant Professor

Publications

Us Patents

Fault-And Variation-Tolerant Energy - And Area-Efficient Links For Network-On-Chips

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US Patent:
20110191646, Aug 4, 2011
Filed:
Apr 6, 2009
Appl. No.:
12/922948
Inventors:
Ahmed Louri - Tucson AZ, US
Janet Meiling Wang Roveda - Tucson AZ, US
Avinash K. Kodi - Athens OH, US
Ashwini Sarathy - Hillsboro OR, US
Assignee:
on behalf of the University of Arizona - Tucson AZ
Ohio University - Athens OH
International Classification:
H04L 12/26
G06F 11/07
US Classification:
714746, 370252, 370242, 714E11023
Abstract:
The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.

Method For Inter-Router Dual-Function Energy- And Area-Efficient Links For Network-On-Chips

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US Patent:
20100002581, Jan 7, 2010
Filed:
Apr 6, 2009
Appl. No.:
12/418701
Inventors:
Ahmed Louri - Tucson AZ, US
Janet Meiling Wang Roveda - Tucson AZ, US
Avinash K. Kodi - Athens OH, US
Ashwini Sarathy - Hillsboro OR, US
Assignee:
The Arizona Board of Regents on Behalf of The University of Arizona - Tucson AZ
International Classification:
H04L 12/26
H04L 12/28
US Classification:
370230, 370351
Abstract:
The present invention provides methods for connecting routers and transmitting data along inter-router links within Nework-on-Chip (NoC) architectures.

Fault And Variation Tolerant Energy And Area Efficient Links For Network-On-Chips

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US Patent:
20150263972, Sep 17, 2015
Filed:
May 13, 2015
Appl. No.:
14/711469
Inventors:
- Tucson AZ, US
- Athens OH, US
Avinash K. Kodi - Athens OH, US
Ashwini Sarathy - Hillsboro OR, US
International Classification:
H04L 12/891
H04L 12/26
G06F 11/08
H04L 12/801
Abstract:
The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.
Avinash Karanth Kodi from Canal Winchester, OH, age ~47 Get Report