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Atul C Ajmera

from Wappingers Falls, NY
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Connected to:
Bhavine Ajmera, 47Monika Ajmera, 44Pratik Ajmera, 43Vishal J Ajmera, 42Vivek Ajmera, 42Kishor G Ajmere, 82Nirav Ajmeri, 39Parvez D Ajmeri, 42Henry Ajo, 42Caroline Ajo-Franklin, 49

Atul Ajmera Phones & Addresses

  • 22 Elizabeth Ter, Wappingers Falls, NY 12590 (845) 298-7154
  • Edison, NJ
  • 22 Elizabeth Ter, Wappingers Falls, NY 12590 (718) 536-0341

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Publications

Us Patents

Low Dielectric Constant Sidewall Spacer Using Notch Gate Process

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US Patent:
6437377, Aug 20, 2002
Filed:
Jan 24, 2001
Appl. No.:
09/768525
Inventors:
Atul C. Ajmera - Wappingers Falls NY
Victor Ku - Tarrytown NY
Dominic J. Schepis - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2710
US Classification:
257204, 257408, 257336
Abstract:
A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.

Surface Engineering To Prevent Epi Growth On Gate Poly During Selective Epi Processing

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US Patent:
6440807, Aug 27, 2002
Filed:
Jun 15, 2001
Appl. No.:
09/882095
Inventors:
Atul C. Ajmera - Wappingers Falls NY
Dominic J. Schepis - Wappingers Falls NY
Michael D. Steigerwalt - Newburgh NY
Assignee:
International Business Machines Corporation - Armonk CA
International Classification:
H01L 21336
US Classification:
438300, 438230, 438303, 438305, 438520, 438528, 438595, 438592, 438976
Abstract:
The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

Cmos Structure With Non-Epitaxial Raised Source/Drain And Self-Aligned Gate And Method Of Manufacture

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US Patent:
6566198, May 20, 2003
Filed:
Mar 29, 2001
Appl. No.:
09/821520
Inventors:
Heemyong Park - LaGrangeville NY
Fariborz Assaderaghi - Mahopac NY
Atul C. Ajmera - Wappingers Falls NY
Ghavam G. Shahidi - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
US Classification:
438259, 438480, 438270, 438271, 438589, 257330
Abstract:
A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.

Method Of Improving Gate Activation By Employing Atomic Oxygen Enhanced Oxidation

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US Patent:
6566210, May 20, 2003
Filed:
Jul 13, 2001
Appl. No.:
09/905233
Inventors:
Atul C. Ajmera - Wappingers Falls NY
Omer H. Dokumaci - Wappingers Falls NY
Bruce B. Doris - Brewster NY
Oleg Gluschenkov - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
US Classification:
438303, 438305, 438306, 257344
Abstract:
The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0. 1, preferably 0. 05, m or less.

Self-Aligned Silicide (Salicide) Process For Strained Silicon Mosfet On Sige And Structure Formed Thereby

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US Patent:
6503833, Jan 7, 2003
Filed:
Nov 15, 2000
Appl. No.:
09/712264
Inventors:
Atul Champaklal Ajmera - Wappingers Falls NY
Cyril Cabral, Jr. - Ossining NY
Roy Arthur Carruthers - Stormville NY
Kevin Kok Chan - Staten Island NY
Guy Moshe Cohen - Mohegan Lake NY
Paul Michael Kozlowski - Hopewell Junction NY
Christian Lavoie - Ossining NY
Joseph Scott Newbury - Tarrytown NY
Ronnen Andrew Roy - Ossining NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2144
US Classification:
438682, 438683, 438655, 438656, 438664
Abstract:
A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si alloy, and selectively etching the unreacted Si.

Method For Forming Notch Gate Having Self-Aligned Raised Source/Drain Structure

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US Patent:
6506649, Jan 14, 2003
Filed:
Mar 19, 2001
Appl. No.:
09/811706
Inventors:
Ka Hing Fung - Beacon NY
Atul C. Ajmera - Wappingers Falls NY
Victor Ku - Tarrytown NY
Dominic J. Schepis - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
US Classification:
438300, 438182, 438197, 438286, 438303, 438306, 438592, 438595, 438652
Abstract:
An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance. The method of constructing such a structure includes the steps of: forming a notch gate on a top surface of a substrate; covering the notch gate and the top surface of the substrate with a conformal dielectric film; etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; implanting doping to form a drain-source area; forming spacers on the vertical walls of the notch gate; and forming a salicide on the notch gate and on the source and drain areas. The MOSFET device may be alternately be built without the formation of spacers.

Method Of Integrating Substrate Contact On Soi Wafers With Sti Process

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US Patent:
6521947, Feb 18, 2003
Filed:
Jan 28, 1999
Appl. No.:
09/239327
Inventors:
Atul Ajmera - Wappingers Falls NY
Effendi Leobandung - Wappingers Falls NY
Werner Rausch - Stormville NY
Dominic J. Schepis - Wappingers Falls NY
Ghavam G. Shahidi - Elmsford NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2701
US Classification:
257347, 257508
Abstract:
A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.

Method Of Forming An Oxide Film On A Gate Side Wall Of A Gate Structure

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US Patent:
6605521, Aug 12, 2003
Filed:
Oct 8, 2002
Appl. No.:
10/265729
Inventors:
Atul C. Ajmera - Wappingers Falls NY
Karanam Balasubramanyam - Hopewell Junction NY
Tomio Katata - Yokohama, JP
Shang-Bin Ko - Poughkeepsie NY
Assignee:
Kabushiki Kaisha Toshiba - Kawasaki
International Business Machines Corporation - Armonk NY
International Classification:
H01L 214763
US Classification:
438595
Abstract:
In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.
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Atul C Ajmera from Wappingers Falls, NY Get Report