Search

Asmita Saha

from Hillsboro, OR
Age ~50
Get Report
Also known as:
Saha Asmita
Related to:
Devashree Saha, 50
Connected to:
Ajay Saha, 41Ananda J Saha, 82Aninda K Saha, 33Anup K Saha, 61Anupama Saha, 41Anurag Saha, 36Apurba K Saha, 67Arindom Saha, 52Ashok K Saha, 73Ayantika Saha, 42

Asmita Saha Phones & Addresses

  • Hillsboro, OR
  • 411 Salisbury St, West Lafayette, IN 47906 (765) 746-0147 (765) 743-4717
  • W Lafayette, IN

Work

Company: Intel corporation Mar 2012 Position: Staff device engineer

Education

Degree: Ph.D School / High School: Purdue University 2001 to 2006 Specialities: Semiconductor Devices

Skills

Semiconductors • Cmos • Ic • Jmp • Process Integration • Thin Films • Silicon • Semiconductor Industry • Yield • Vlsi • Asic • Integrated Circuits • Device Physics • Semiconductor Manufacturing • Physics • Device Characterization

Interests

Education

Industries

Semiconductors

Resumes

Resumes

Asmita Saha Photo 1

Iit Kharagpur

View page
Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation since Mar 2012
Staff Device Engineer
Intel Corporation Apr 2007 - Mar 2012
Sr. Device Engineer (Process Technology Development Engg.)
Education:
Purdue University 2001 - 2006
Ph.D, Semiconductor Devices IIT Kharagpur
Master of Technology (M.Tech.), Electronics and Electrical communication Engg. Jadavpur University
Bachelor of Engineering (B.E.), Electronics and Telecommunication Engg.
Skills:
Semiconductors
Cmos
Ic
Jmp
Process Integration
Thin Films
Silicon
Semiconductor Industry
Yield
Vlsi
Asic
Integrated Circuits
Device Physics
Semiconductor Manufacturing
Physics
Device Characterization
Interests:
Education

Publications

Us Patents

Sic Power Dmosfet With Self-Aligned Source Contact

View page
US Patent:
8035112, Oct 11, 2011
Filed:
Apr 23, 2009
Appl. No.:
12/429176
Inventors:
James A. Cooper - West Lafayette IN, US
Asmita Saha - Hillsboro OR, US
Assignee:
Purdue Research Foundation - West Lafayette IN
International Classification:
H01L 21/0312
US Classification:
257 77, 257 76, 438142
Abstract:
An intermediate product in the fabrication of a MOSFET, including a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof; a first oxide layer on said upper surface of said drift layer; a plurality of polysilicon gates above said first oxide layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions; an oxide layer over said first source region of greater thickness than said first oxide layer; and, an oxide layer over said first gate of substantially greater thickness than said oxide layer over said first source region.

High-Voltage Power Semiconductor Device

View page
US Patent:
20060192256, Aug 31, 2006
Filed:
Jan 23, 2006
Appl. No.:
11/338007
Inventors:
James Cooper - West Lafayette IN, US
Asmita Saha - West Lafayette IN, US
International Classification:
H01L 29/76
H01L 29/94
H01L 31/00
US Classification:
257401000
Abstract:
A semiconductor device, such as a metal-oxide semiconductor field-effect transistor, includes a semiconductor substrate, a drift layer formed on the substrate, a first and a second source region, and a JFET region defined between the first and the second source regions. The JFET region may have a short width and/or a higher concentration of impurities than the drift layer. The semiconductor device may also include a current spreading layer formed on the drift layer. The current spreading layer may also have a higher concentration of impurities than the drift layer.
Control profile
Asmita Saha from Hillsboro, OR, age ~50 Get Report