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Asit Shankar

from Murphy, TX
Age ~48
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Also known as:
Asitsura Verma
Phone and address:
626 Gene Autry Ln, Plano, TX 75094
(972) 429-5895
Related to:
Surabhi Verma, 46Ajay Shankar, 76Asim ShankarMamta Shankar, 73
Connected to:
Aditi Shankardass, 54Ajit Shankaranarayanan, 52Akila Shankar, 58Amulya T Shankar, 31Anne B Shankar, 73Aswini K Shankar, 68Babu Shankar, 63Bhawana S Shankar, 50Diya Shankardass, 54Harish Shankaran, 48

Asit Shankar Phones & Addresses

  • 626 Gene Autry Ln, Murphy, TX 75094 (972) 429-5895
  • 540 Buckingham Rd, Richardson, TX 75081 (972) 238-7852
  • Peoria, IL
  • College Station, TX
  • Colton, TX

Resumes

Resumes

Asit Shankar Photo 1

Senior Design Engineer

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Location:
Richardson, TX
Industry:
Semiconductors
Work:
Analog Devices
Senior Design Engineer
Linear Technology
Ic Design Engineer
Texas Instruments Jan 2001 - Oct 2006
Ic Designer
Texas A&M University 2000 - 2000
Research Assistant
Texas A&M University 1999 - 2000
Teaching Assistant
Education:
Texas A&M University 1998 - 2001
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Delhi 1994 - 1998
Bachelors, Bachelor of Technology, Electrical Engineering
Skills:
Mixed Signal
Analog Circuit Design
Ic
Analog
Semiconductors
Integrated Circuit Design
Asic
Circuit Design
Soc
Cmos
Vlsi
Cadence Virtuoso
Low Power Design
Eda
Pll
Bicmos
Electronics
Asit Shankar Photo 2

Asit Shankar

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Publications

Us Patents

All-Digital Phase-Locked Loop For A Digital Pulse-Width Modulator

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US Patent:
7425874, Sep 16, 2008
Filed:
Jun 30, 2006
Appl. No.:
11/427853
Inventors:
Lars Risbo - Kobernhavn Ø, DK
Asit Shankar - Richardson TX, US
Josey George Angilivelil - Sachse TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03L 7/093
US Classification:
331 1A, 331 17, 375376
Abstract:
A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.

Method And System For Transitioning Between Operation States In An Output System

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US Patent:
7554390, Jun 30, 2009
Filed:
Dec 20, 2007
Appl. No.:
11/961144
Inventors:
Asit Shankar - Murphy TX, US
Klaus Krogsgaard - Lyngby, DK
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 3/38
US Classification:
330 10, 330251, 330291, 330 51
Abstract:
A closed loop amplifier system comprising a modulator that provides a pulse-width modulated (PWM) output signal based on an input signal, the modulator having a variable closed loop transfer function. The system also comprises a ramp generator that provides a ramp signal to the modulator, the variable closed loop transfer function of the modulator varying as a function of the ramp signal. The system further comprises a controller that controls the ramp generator to provide the ramp signal to adjust the variable closed loop transfer function during transitions between operating states of the amplifier system.

High Performance Analog Charge Pumped Phase Locked Loop (Pll) Architecture With Process And Temperature Compensation In Closed Loop Bandwidth

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US Patent:
20060071716, Apr 6, 2006
Filed:
Sep 30, 2004
Appl. No.:
10/955064
Inventors:
Lieyi Fang - Plano TX, US
Asit Shankar - Richardson TX, US
Lars Risbo - Copenhagen, DK
International Classification:
H03L 7/00
US Classification:
331016000
Abstract:
The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)() with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product K*Iindependent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump ().

Amplifier With Reduced Power Consumption And Improved Slew Rate

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US Patent:
20200228066, Jul 16, 2020
Filed:
Apr 19, 2019
Appl. No.:
16/389435
Inventors:
- Limerick, IE
Asit Shankar - Murphy TX, US
International Classification:
H03F 1/22
H03F 3/45
H03F 1/02
Abstract:
An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.
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Asit Shankar from Murphy, TX, age ~48 Get Report