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Ashutosh A Goyal

from Austin, TX
Age ~56
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Also known as:
Ash A Goyal, Oayl G Ashutosh, Archana Goyal, Ashutosh Jain, Ashutosh Goval, Archana Jain, Goyal Ash, Jain Ash
Phone and address:
14819 Calaveras Dr, Austin, TX 78717
(512) 244-9894
Related to:
Sumit JainSally Dixon, 79Vijaya Katragadda, 61Anila KatragaddaSally Mcdowell, 64Tracy Ash, 77
Connected to:
Ajay E Goyal, 62Akash V Goyal, 31Anmol Goyal, 33Anup Goyal, 43Archana Goyal, 51Aseem Goyal, 48Brij M Goyal, 44Gaurav Goyal, 50Girish Goyal, 40Hari S Goyal, 82

Ashutosh Goyal Phones & Addresses

  • 14819 Calaveras Dr, Austin, TX 78717 (512) 244-9894
  • Liberty Hill, TX
  • Marble Falls, TX
  • Plano, TX
  • Travis, TX
  • 14819 Calaveras Dr, Austin, TX 78717

Education

Degree: Graduate or professional degree

Publications

Us Patents

Method Of Forcing 1'S And Inverting Sum In An Adder Without Incurring Timing Delay

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US Patent:
7523153, Apr 21, 2009
Filed:
Feb 11, 2005
Appl. No.:
11/057330
Inventors:
Ashutosh Goyal - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 7/507
US Classification:
708714
Abstract:
A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force signal. The two functions are implemented without introducing additional delay.

Inverting Data On Result Bus To Prepare For Instruction In The Next Cycle For High Frequency Execution Units

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US Patent:
7991816, Aug 2, 2011
Filed:
Aug 12, 2008
Appl. No.:
12/189797
Inventors:
Brian William Curran - Saugerties NY, US
Ashutosh Goyal - Austin TX, US
Michael Thomas Vaden - Austin TX, US
David Allan Webber - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 7/38
US Classification:
708490, 708524
Abstract:
A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

Method Of Forcing 1'S And Inverting Sum In An Adder Without Incurring Timing Delay

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US Patent:
8429213, Apr 23, 2013
Filed:
Jan 26, 2009
Appl. No.:
12/360106
Inventors:
Ashutosh Goyal - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 7/50
US Classification:
708206
Abstract:
A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.

Inverting Data On Result Bus To Prepare For Instruction In The Next Cycle For High Frequency Execution Units

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US Patent:
20060184773, Aug 17, 2006
Filed:
Feb 11, 2005
Appl. No.:
11/056894
Inventors:
Brian Curran - Saugerties NY, US
Ashutosh Goyal - Austin TX, US
Michael Vaden - Austin TX, US
David Webber - Poughkeepsie NY, US
International Classification:
G06F 9/44
US Classification:
712221000
Abstract:
A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
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Ashutosh A Goyal from Austin, TX, age ~56 Get Report