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Ashraf K Takla

from Aptos, CA
Age ~68
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Also known as:
Ashraf Living Takla, Ashraf K Takala
Related to:
Amanda Takla, 46Adel Takla Kamel, 45Takla A Kamel, 45Michael A Takla, 33Hoda S Takawa, 71Nadia Takla, 38Hany M Takla, 44Magdy K Takla, 77Victoria K Dunn, 67Ramy Magdy Takla, 46Abel K TaklaAdel K Takla, 75
Connected to:
Magda M Takla, 76Francois K Takle, 84Ginger L Takle, 46Harshavardhan Takle, 55Brian A Takleszyn, 41James P Takleszyn, 35Angela R Taklo, 38Paul D Taklo, 54Besmir Tako, 38Esther N Tako, 40

Ashraf Takla Phones & Addresses

  • Aptos, CA
  • 3238 Capriana Cir, San Jose, CA 95135 (408) 223-6924
  • 3239 Rocky Water Ln, San Jose, CA 95148 (408) 826-4788 (408) 434-1376
  • 2915 Archwood Cir #C112, San Jose, CA 95148 (408) 434-1376
  • 1000 Escalon Ave, Sunnyvale, CA 94085 (408) 434-1376

Work

Company: Veridicom 1998 to 1999 Position: Director: mixed-signal design

Education

Degree: Master of Science, Masters School / High School: San Diego State University 1980 to 1981 Specialities: Electrical Engineering

Skills

Ic • Semiconductors • Pll • Asic • Serdes • Analog • Electronics • Soc • Integrated Circuit Design • Low Power Design • Analog Circuit Design • Cmos • Mixed Signal • Fpga • Vlsi • Embedded Systems • Cadence Virtuoso • Hardware Architecture • Integrated Circuits • System on A Chip • Mipi • Application Specific Integrated Circuits • Phy • Signal Integrity

Languages

English

Industries

Semiconductors

Public records

Vehicle Records

Ashraf Takla

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Address:
3238 Capriana Cir, San Jose, CA 95135
Phone:
(408) 666-9853
VIN:
JN1BY1APXBM323960
Make:
INFINITI
Model:
M37
Year:
2011

Resumes

Resumes

Ashraf Takla Photo 1

President And Chief Executive Officer

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Location:
3238 Capriana Cir, San Jose, CA 95135
Industry:
Semiconductors
Work:
Veridicom 1998 - 1999
Director: Mixed-Signal Design
Mixel, Inc. 1998 - 1999
President and Chief Executive Officer
Hitachi Micro Systems 1992 - 1997
Director of Mixed-Signal Design
Pmc-Sierra 1984 - 1986
Senior Mixed-Signal Design Engineer
American Microsystems 1982 - 1984
Circuit Deisgn Engineer
Education:
San Diego State University 1980 - 1981
Master of Science, Masters, Electrical Engineering San Diego State University 1978 - 1979
Bachelors, Bachelor of Science, Electrical Engineering Cairo University 1973 - 1977
Bachelors, Bachelor of Science, Electrical Engineering San Diego State University
Masters, Master of Science In Electrical Engineering, Electronics
Skills:
Ic
Semiconductors
Pll
Asic
Serdes
Analog
Electronics
Soc
Integrated Circuit Design
Low Power Design
Analog Circuit Design
Cmos
Mixed Signal
Fpga
Vlsi
Embedded Systems
Cadence Virtuoso
Hardware Architecture
Integrated Circuits
System on A Chip
Mipi
Application Specific Integrated Circuits
Phy
Signal Integrity
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ashraf Takla
President
Mixel
Semiconductors and Related Devices
3238 Capriana Cir, San Jose, CA 95135
Website: mixl.com
Ashraf Takla
President
Mixel, Inc
Business Services
4423 Fortran Ct Ste 170, San Jose, CA 95135
Ashraf Takla
President
MIXEL, INC
Semiconductors & Related Devices Mfg · Semiconductor Devices (Manufac
3238 Capriana Cir, San Jose, CA 95135
(408) 274-2736
Ashraf Takla
President
Mixel
Semiconductors and Related Devices
3238 Capriana Cir, San Jose, CA 95135
Website: mixl.com
Ashraf Takla
President
Mixel, Inc
Business Services
4423 Fortran Ct Ste 170, San Jose, CA 95135

Publications

Us Patents

Hybrid Phase-Locked Loop Employing Analog And Digital Loop Filters

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US Patent:
59784253, Nov 2, 1999
Filed:
May 23, 1997
Appl. No.:
8/863039
Inventors:
Ashraf K. Takla - San Jose CA
Assignee:
Hitachi Micro Systems, Inc. - San Jose CA
International Classification:
H03D 324
US Classification:
375374
Abstract:
The invention provides a hybrid phase-locked loop (PLL) containing digital and analog portions for digital and analog adjustments, respectively, of an output signal. The hybrid PLL is simple in design. Off-the-shelf controlled oscillators, such as a current controlled oscillator (CCO) can be used with this hybrid PLL. The digital and the analog portions of the hybrid PLL are separate from the controlled oscillator. The digital portion is for a first adjustment of the frequency of the output signal, such as during a calibration. The analog portion is for fine phase and frequency adjustment of the output signal.

Phase Locked Loop With High And/Or Low Frequency Limit Detectors For Preventing False Lock On Harmonics

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US Patent:
45904405, May 20, 1986
Filed:
Jul 6, 1984
Appl. No.:
6/628608
Inventors:
Yusuf A. Haque - San Jose CA
Ashraf K. Takla - San Jose CA
Assignee:
American Microsystems, Inc. - Santa Clara CA
International Classification:
H03L 706
US Classification:
331 17
Abstract:
A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V. sub. out) which is compared with the input signal (V. sub. in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop. If the output frequency of voltage controlled oscillator is below the predefined frequency range, the limiter circuit provides a high voltage output signal to the control input lead of the VCO in order to pull the input voltage of the voltage controlled oscillator to a voltage which corresponds with the proper operating frequency range of the phase locked loop.

Method And Apparatus For Adaptive Clock Deskewing

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US Patent:
55700543, Oct 29, 1996
Filed:
Sep 26, 1994
Appl. No.:
8/312355
Inventors:
Ashraf K. Takla - San Jose CA
Assignee:
Hitachi Micro Systems, Inc. - San Jose CA
International Classification:
H03K 513
H03K 301
US Classification:
327292
Abstract:
A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors. The proximal end of one of the pair of conductors is coupled to the output of a delay line and receives a phase corrected version of the system clock signal. The distal end of this conductor is coupled to the load device at a clock connection node. The clock connection node is fed back to the phase correction circuit via the other one of the pair of conductors. The first and second conductors have equal path lengths in order to provide equal propagation delays. The clock signal fed back from the load device node is coupled as a feedback input to a three input phase detector circuit. The other two inputs are the clock signal output from the phase correction circuit delay line and the system clock signal. Each phase correction circuit includes a charge pump coupled to the output of the phase detector circuit, and a loop filter coupled to the output of the charge pump.

Method And Apparatus For Averaging Clock Skewing In Clock Distribution Network

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US Patent:
55700535, Oct 29, 1996
Filed:
Sep 26, 1994
Appl. No.:
8/312026
Inventors:
Ashraf K. Takla - San Jose CA
Assignee:
Hitachi Micro Systems, Inc. - San Jose CA
International Classification:
H03L 700
H03L 718
US Classification:
327292
Abstract:
A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line.

Method And Apparatus For Fast Clock Recovery Phase-Locked Loop With Training Capability

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US Patent:
60441232, Mar 28, 2000
Filed:
Oct 17, 1996
Appl. No.:
8/733869
Inventors:
Ashraf K. Takla - San Jose CA
Assignee:
Hitachi Micro Systems, Inc. - San Jose CA
International Classification:
H03D 324
US Classification:
375376
Abstract:
A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.

Method And Apparatus For Fast Clock Recovery Phase-Locked Loop With Training Capability

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US Patent:
62953273, Sep 25, 2001
Filed:
Aug 10, 1999
Appl. No.:
9/370606
Inventors:
Ashraf K. Takla - San Jose CA
Assignee:
Hitachi Micro Systems, Inc. - San Jose CA
International Classification:
H03D 324
US Classification:
375375
Abstract:
A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.

Differential Physical Layer Device With Testing Capability

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US Patent:
20200097378, Mar 26, 2020
Filed:
Apr 1, 2019
Appl. No.:
16/372315
Inventors:
Ashraf K. Takla - San Jose CA, US
International Classification:
G06F 11/22
Abstract:
A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.
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Ashraf K Takla from Aptos, CA, age ~68 Get Report