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Ashraf Elsharif Phones & Addresses

  • Austin, TX
  • Astoria, NY
  • Flushing, NY

Work

Company: Ibm May 2015 Position: Logic design engineer

Education

Degree: Master of Science, Masters School / High School: New York University - Polytechnic School of Engineering 2012 to 2015 Specialities: Computer Engineering

Skills

Microcontrollers • Embedded Systems • Vhdl • Linux • Programming • C++ • Medical Devices • Electrophysiology • Low Power Design • Java • Fpga Prototyping • Digital Ic Design • Computer Hardware • Windows • Pcb Layout Design • Allegro Pcb • Microsoft Excel • Javase • Embedded Software • Testing • Microsoft Office • Algorithms • Pcb Design • Matlab • Cisco Ios • C • Tcl • Soldering • Xilinx Ise • Code Composer Studio • Arm Assembly • Altera Quartus • Lattice Icecube2 • Wireshark • Cadence Virtuoso • Cadence Spectre • Git • Oscilloscope • Logic Analyzer • Spectral Analysis • Msp430 • Arm Cortex M4 • Spi • Uart • I2C • Tcp/Ip • Arm • Device Drivers • Debugging

Languages

Arabic • English

Industries

Computer Hardware

Resumes

Resumes

Ashraf Elsharif Photo 1

Logic Design Engineer

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Location:
Austin, TX
Industry:
Computer Hardware
Work:
Ibm
Logic Design Engineer

Nyu Tandon School of Engineering Sep 2013 - Jan 2015
Teaching Assistant

Nyu Tandon School of Engineering Jun 2013 - Jan 2015
Research Assistant - Medical Device Lab - Ece Department

Motorola Solutions Jun 2014 - Aug 2014
Embedded Software Engineering Intern

Systel Jun 2009 - Jun 2009
Trainee
Education:
New York University - Polytechnic School of Engineering 2012 - 2015
Master of Science, Masters, Computer Engineering
Ain Shams University 2007 - 2012
Bachelors, Bachelor of Science, Engineering
Skills:
Microcontrollers
Embedded Systems
Vhdl
Linux
Programming
C++
Medical Devices
Electrophysiology
Low Power Design
Java
Fpga Prototyping
Digital Ic Design
Computer Hardware
Windows
Pcb Layout Design
Allegro Pcb
Microsoft Excel
Javase
Embedded Software
Testing
Microsoft Office
Algorithms
Pcb Design
Matlab
Cisco Ios
C
Tcl
Soldering
Xilinx Ise
Code Composer Studio
Arm Assembly
Altera Quartus
Lattice Icecube2
Wireshark
Cadence Virtuoso
Cadence Spectre
Git
Oscilloscope
Logic Analyzer
Spectral Analysis
Msp430
Arm Cortex M4
Spi
Uart
I2C
Tcp/Ip
Arm
Device Drivers
Debugging
Languages:
Arabic
English

Publications

Us Patents

Ownership Tracking Updates Across Multiple Simultaneous Operations

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US Patent:
20180336134, Nov 22, 2018
Filed:
May 18, 2017
Appl. No.:
15/598837
Inventors:
- ARMONK NY, US
Timothy C. Bronson - Round Rock TX, US
Ashraf ElSharif - Austin TX, US
Kenneth D. Klapproth - Austin TX, US
Vesselina K. Papazova - Highland NY, US
Guy G. Tracy - AUSTIN TX, US
International Classification:
G06F 12/0817
G06F 12/0891
Abstract:
Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.

Ownership Tracking Updates Across Multiple Simultaneous Operations

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US Patent:
20180336135, Nov 22, 2018
Filed:
Nov 20, 2017
Appl. No.:
15/817717
Inventors:
- Armonk NY, US
Timothy C. Bronson - Round Rock TX, US
Ashraf ElSharif - Austin TX, US
Kenneth D. Klapproth - Austin TX, US
Vesselina K. Papazova - Highland NY, US
Guy G. Tracy - AUSTIN TX, US
International Classification:
G06F 12/0817
G06F 12/0891
Abstract:
Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.
Ashraf M Elsharif from Austin, TX, age ~34 Get Report