Asheesh Bhardwaj

20190278596, Sep 12, 2019

May 23, 2019

16/420457

- Dallas TX, US
Asheesh Bhardwaj - Allen TX, US
Son Hung Tran - Murphy TX, US
Timothy David Anderson - University Park TX, US

G06F 9/30
G06F 9/345
G06F 9/38
G06F 11/10
G06F 9/32
G06F 12/0875
G06F 12/0897
G06F 11/00

Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

20180349096, Dec 6, 2018

Jun 1, 2018

15/995647

- Dallas TX, US
Asheesh BHARDWAJ - Allen TX, US
Tarek Aziz LAHLOU - Plano TX, US
William Franklin LEVEN - Dallas TX, US

G06F 7/36
G06F 9/30
G06F 7/24
G06F 7/32

A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.

20180246669, Aug 30, 2018

Feb 27, 2018

15/907042

- Dallas TX, US
Asheesh Bhardwaj - Allen TX, US

G06F 3/06

A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.