Asadd M Hosein

8551886, Oct 8, 2013

Apr 9, 2008

12/100118

Kyle P. Hunt - Richardson TX, US
Leila Elvira Noriega - Forney TX, US
Billy Alan Wofford - Dallas TX, US
Asadd M. Hosein - Plano TX, US
Binghua Hu - Plano TX, US
Xinfen Chen - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/302
H01L 21/3105

438692, 438300, 438633, 438689, 438697, 438734, 438733, 438722, 438723, 438724, 257500, 257501, 257506, 257E21214, 257E21218, 257E21243, 257E21244, 257E21245, 257E21246, 257E21303, 257E21304, 257E21311, 257E29261

A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

20040007755, Jan 15, 2004

Jul 12, 2002

10/193959

Binghua Hu - Plano TX, US
Betty Mercer - Plano TX, US
Pushpa Mahalingam - Richardson TX, US
Asadd Hosein - Plano TX, US
John Arch - Richardson TX, US
C. Thompson - Highland Village TX, US

Texas Instruments Incorporated

H01L029/00

257/506000

In one embodiment of the present invention, a contact structure of a semiconductor device within an integrated circuit includes an active region, the active region having been defined using a mask provided on a substrate. The contact structure further includes an isolation region adjacent the active region and including a field oxide: the field oxide having been grown by exposure of the substrate to a thermal process and an oxygen-containing gas; a film having been formed on a top surface of the mask during exposure to the thermal process and oxygen-containing gas; a dry etching process having been performed to substantially remove the film from the top surface of the mask and to remove a top portion of the field oxide in the isolation region; and a wet etching process having been performed to substantially remove any portion of the mask remaining after the dry etching process.

20040150065, Aug 5, 2004

Jan 20, 2004

10/761691

Binghua Hu - Plano TX, US
Betty Mercer - Plano TX, US
Pushpa Mahalingam - Richardson TX, US
Asadd Hosein - Plano TX, US
John Arch - Richardson TX, US
C. Thompson - Highland Village TX, US

H01L029/00

257/499000

In one embodiment of the present invention, a contact structure of a semiconductor device within an integrated circuit includes an active region, the active region having been defined using a mask provided on a substrate. The contact structure further includes an isolation region adjacent the active region and including a field oxide: the field oxide having been grown by exposure of the substrate to a thermal process and an oxygen-containing gas; a film having been formed on a top surface of the mask during exposure to the thermal process and oxygen-containing gas; a dry etching process having been performed to substantially remove the film from the top surface of the mask and to remove a top portion of the field oxide in the isolation region; and a wet etching process having been performed to substantially remove any portion of the mask remaining after the dry etching process.

20080242007, Oct 2, 2008

Mar 30, 2007

11/694700

Kyle Hunt - Richardson TX, US
Neel Bhatt - Allen TX, US
Asadd M. Hosein - Plano TX, US
Brian L. Vialpando - Dallas TX, US
William R. Morrison - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/28

438128, 438296, 438421, 438423, 438697

The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features () over a substrate (), and then forming a layer of material () over the semiconductor features (). This method further includes selectively etching portions of the layer of material () based upon a density or size of the semiconductor features () located thereunder, and then polishing remaining portions of the layer of material ().