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Arvind Bhaskar Patwardhan

from Newark, CA
Age ~65
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Also known as:
Arvind B Patwardhan, Arvind D Patwardhan, Arvi Patwardhan
Phone and address:
37391 Fowler St, Newark, CA 94560
(510) 790-2993
Related to:
Lynn Waters, 61Sumedha A Patwardhan, 62Jeorge L Logan, 59Sumedha Arvind Patwardham, 62Anvita A Patwardhan, 30
Connected to:
Aditi A Patwardhan, 40Alka W Patwardhan, 77Harshad S Patwardhan, 54Kaustubh Patwardhan, 39Makarand V Patwardhan, 53Manjiri Patwardhan, 50Parag V Patwardhan, 45Prakash N Patwardhan, 65Rucha V Patwardhan, 35Manish Patwari, 58

Arvind Patwardhan Phones & Addresses

  • 37391 Fowler St, Newark, CA 94560 (510) 790-2993
  • 1561 Rue Avati, San Jose, CA 95131 (408) 259-1264 (408) 929-3898
  • Santa Clara, CA
  • Alameda, CA
  • Fremont, CA
  • 37391 Fowler St, Newark, CA 94560 (559) 270-6512

Work

Company: Amd May 2018 Position: Member of technical staff

Education

Degree: High school graduate or higher

Emails

s***[email protected]

Resumes

Resumes

Arvind Patwardhan Photo 1

Member Of Technical Staff

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Location:
Newark, CA
Work:
Amd
Member of Technical Staff

Publications

Us Patents

System And Method For Mpeg Reverse Play Through Dynamic Assignment Of Anchor Frames

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US Patent:
6473558, Oct 29, 2002
Filed:
Jun 26, 1998
Appl. No.:
09/105938
Inventors:
Scarlett Wu - Hillsborough CA
Arvind Patwardhan - San Jose CA
Osamu Takiguchi - Tokyo, JP
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 5783
US Classification:
386 68, 386125, 386126
Abstract:
A method and system for displaying a series of video frames in reverse order. The video frames are received in groups of pictures (GOPs) from a storage medium. The method comprises steps of (a) decoding and storing a number of frames from an initial GOP into frame buffers according to an ordering of the frame buffers, (b) displaying the stored frames according to the reverse ordering of the frame buffers, (c) decoding and storing a number of frames from a first preceding GOP according to the reverse ordering of the frame buffers, (d) displaying the stored frames according to the ordering of the frame buffers, (e) decoding and storing a number of frames from a second preceding GOP according to the ordering of the frame buffers, and (f) repeating steps (b)-(e),for prior first and second preceding GOPs.

Dynamic Memory Arbitration In An Mpeg-2 Decoding System

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US Patent:
6704846, Mar 9, 2004
Filed:
Jun 26, 1998
Appl. No.:
09/105492
Inventors:
Scarlett Z. Wu - Hillsborough CA
Darren D. Neuman - San Jose CA
Arvind B. Patwardhan - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1200
US Classification:
711150
Abstract:
A video decoding system includes an embedded microcontroller that provides memory arbitration in addition to processing and control functions. The microcontroller architecture provides a first-in, first-out (FIFO) queue for storing memory access instructions and a processing logic for executing software instructions. The microcontroller processing logic determines which components within the decoding system need access to memory and stores a sequence of memory access instructions into the FIFO queue. Each memory access instruction is associated with one decoder component. When main memory becomes available, a memory access instruction is dequeued from the FIFO and transmitted to the associated decoder component, which is then permitted to access memory. The microcontroller receives indicator signals from the decoder components that indicate when the decoder components have finished accessing memory and, thus, when the memory device is available for subsequent transactions.

Methods And Apparatuses For Synchronizing Data Conversion Of Sonet Framed Data

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US Patent:
6741615, May 25, 2004
Filed:
Sep 14, 2000
Appl. No.:
09/661496
Inventors:
Arvind Bhaskar Patwardhan - San Jose CA
Sunil Tomar - Fremont CA
Srinivasarao Neelamraju - Pleasanton CA
Assignee:
Ciena Corporation - Linthicum MD
International Classification:
H04J 306
US Classification:
370514, 370516, 370539, 375371
Abstract:
A serial data signal having a predetermined sequence to indicate a start of a frame of data is received. The serial data signal is compared to a plurality of values. The plurality of values include the predetermined sequence and one or more values representing logical rotations of the predetermined sequence. A match signal is generated in response to the serial data signal matching one of the plurality of values.

Methods And Apparatuses For Serial Transfer Of Sonet Framed Data Between Components Of A Sonet System

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US Patent:
6944190, Sep 13, 2005
Filed:
Sep 14, 2000
Appl. No.:
09/660837
Inventors:
Sunil Tomar - Fremont CA, US
Arvind Bhaskar Patwardhan - Newark CA, US
Srinivasarao Neelamraju - Pleasanton CA, US
Assignee:
Ciena Corporation - Linthicum MD
International Classification:
H04J003/04
US Classification:
370535, 370539, 370541
Abstract:
A plurality of transmission circuits transmit data over one or more output lines. A plurality of receiving circuits receive data over one or more of a set of input lines A plurality of parallel-serial conversion circuits coupled to the plurality of transmission circuits and to the plurality of receiving circuits, the plurality of conversion circuits to convert parallel signals to one or more sets of serial signals and to send the converted serial signals to one or more corresponding transmission circuits, and to receive one or more sets of serial signals from one or more of the receiving circuits and to convert the serial signals to parallel signals.

Audio Decoder Bypass Module For Communicating Compressed Audio To External Components

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US Patent:
61190926, Sep 12, 2000
Filed:
Jun 26, 1998
Appl. No.:
9/105614
Inventors:
Arvind Patwardhan - San Jose CA
Kosala Abeywickrema - San Jose CA
Sophia Kao - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G10L 1900
G10L 2104
US Classification:
704503
Abstract:
A multimedia decoder is provided with an audio decoder bypass module for forwarding undecoded audio bitstreams directly to external system components. In one embodiment, the multimedia decoder includes an audio decoder, and a bypass module. The audio decoder operates on the data in an audio bitstream buffer to convert at least a portion of the audio bitstream into a set of digital audio signals. The bypass module is configured to provide the full information content of the audio bitstream to an external system component which may be able to convert a greater portion of the audio bitstream into a second set of digital audio signals. As the audio decoder and bypass module each retrieve data from the audio bitstream buffer, they each use a pointer to track which location of the buffer to access next. The bypass module maintains a loose synchronization with the audio decoder by calculating the difference between the pointers and transmitting the current audio packet only if the magnitude of the difference doesn't exceed a predetermined threshold. If the bypass module is lagging behind the audio decoder by more than the threshold amount, then it skips ahead to the next audio packet.

Computer Memory Interface Having A Memory Controller That Automatically Adjusts The Timing Of Memory Interface Signals

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US Patent:
61377341, Oct 24, 2000
Filed:
Mar 30, 1999
Appl. No.:
9/281381
Inventors:
Brian F. Schoner - Fremont CA
Arvind B. Patwardhan - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G11C 700
US Classification:
365194
Abstract:
A memory controller features programmable delay buffers that allow the memory interface signals to be automatically adjusted. By fine tuning the delay values, the memory controller can compensate for impedance characteristics that affect the memory interface timing. The memory controller includes a built-in self test mode, in which it runs a series of memory tests using a plurality of different delay combinations for the delay buffers. After running the built-in self test, the memory controller programs the delay buffers to values which allow the memory transactions to occur without errors, ensuring optimal memory interface timing.

Method For Decompressing Linear Pcm And Ac3 Encoded Audio Gain Value

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US Patent:
61121703, Aug 29, 2000
Filed:
Jun 26, 1998
Appl. No.:
9/105718
Inventors:
Arvind Patwardhan - San Jose CA
Ning Xue - Fremont CA
Takumi Nagasako - Tokyo, JP
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G10L 1900
G10L 2104
US Classification:
704212
Abstract:
An audio decoder which includes a coefficient memory and an arithmetic logic unit (ALU) can implement an efficient method for calculating a gain value specified by a range control field. In one embodiment, the audio decoder comprises coefficient memory, an ALU, frame control logic, and ALU control logic. The frame control logic extracts a range control field value from an audio packet header and provides it to the ALU control logic. The ALU control logic takes the binary representation of the range control field value and uses it to provide a sequence of addresses to the coefficient memory. In response to the sequence of addresses, the coefficient memory provides a sequence of pre-calculated factors to the ALU. The ALU control logic further directs the ALU to determine the product of the pre-calculated factors in the sequence. As a final step in finding the gain value, the ALU control logic may provide a shift instruction to the ALU.

Detection Mechanism For Video Channel Underflow In Mpeg-2 Video Decoding

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US Patent:
61608475, Dec 12, 2000
Filed:
Jun 26, 1998
Appl. No.:
9/106049
Inventors:
Scarlett Wu - Hillsborough CA
Arvind Patwardhan - San Jose CA
Youichi Obana - Tokyo, JP
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 712
H04N 1102
H04N 1104
US Classification:
3752401
Abstract:
A method and system for displaying a series of video frames so that picture corruption from video channel underflows is avoided. The method comprises the steps of receiving a data stream with compressed video data for the series of video frames, storing the compressed video data in a channel buffer, processing a video frame if sufficient compressed video data for the video frame is stored in the channel buffer, and displaying a preceding video frame if insufficient compressed video data for the video frame is stored in the channel buffer. The system, which displays a series of video frames, also addresses the issue of video channel underflow. The video frames are received as compressed video data in a data stream that also includes size parameters, such as the vbv. sub. -- delay parameter in the frame headers of MPEG frames, for each video frame in the series of video frames. The system comprises an input for receiving a data stream, a channel buffer for storing the compressed video data, a decoder that decodes the compressed video data and provides the decoded video data to a display device, and an underflow detector that compares the amount of compressed video data in the channel buffer to the required amount of compressed video data.
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Arvind Bhaskar Patwardhan from Newark, CA, age ~65 Get Report