Inventors:
Mark B. Trobough - Olympia WA, US
Keshavan K. Tiruvallur - Tigard OR, US
Chinna B. Prudvi - Portland OR, US
Christian E. Iovin - Federal Way WA, US
David W. Grawrock - Aloha OR, US
Jay J. Nejedlo - Wilsonville OR, US
Ashok N. Kabadi - Portland OR, US
Travis K. Goff - Hillsboro OR, US
Evan J. Halprin - Hillsboro OR, US
Kapila B. Udawatta - San Diego CA, US
Jiun Long Foo - Bayan Lepas, MY
Wee Hoo Cheah - Bayan Lepas, MY
Vui Yong Liew - Bukit Mertajam, MY
Selvakumar Raja Gopal - Tapah, MY
Yuen Tat Lee - Bayan Lepas, MY
Samie B. Samaan - West Linn OR, US
Kip C. Killpack - Beaverton OR, US
Neil Dobler - Aloha OR, US
Nagib Z. Hakim - Santa Clara CA, US
Briar Meyer - Cornelius OR, US
William H. Penner - Olympia WA, US
John L. Baudrexl - Olympia WA, US
Russell J. Wunderlich - Livermore CO, US
James J. Grealish - Beaverton OR, US
Kyle Markley - Hillsboro OR, US
Timothy S. Storey - Hillsboro OR, US
Loren J. McConnell - Forest Grove OR, US
Lyle E. Cool - Beaverton OR, US
Mukesh Kataria - Fremont CA, US
Rahima K. Mohammed - San Jose CA, US
Tieyu Zheng - Sammamish WA, US
Yi Amy Xia - Campbell CA, US
Ridvan A. Sahan - Sunnyvale CA, US
Arun R. Ramadorai - Sammamish WA, US
Priyadarsan Patra - Austin TX, US
Edwin E. Parks - Hillsboro OR, US
Abhijit Davare - Hillsboro OR, US
Padmakumar Gopal - Austin TX, US
Bruce Querbach - Beaverton OR, US
Hermann W. Gartler - Portland OR, US
Keith Drescher - Olympia WA, US
Sanjay S. Salem - Portland OR, US
David C. Florey - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
G06F 11/273
Abstract:
An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.