Arthur Abnous

6373900, Apr 16, 2002

Jan 22, 2001

09/767101

Oscar E. Agazzi - Irvine CA
David Kruse - Newport Beach CA
Arthur Abnous - Irvine CA
Mehdi Hatamian - Viejo CA

Broadcom Corporation - Irvine CA

H04L 2534

375288, 375260, 375265

A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.

6459746, Oct 1, 2002

Feb 9, 2001

09/781914

Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Utrecht, NL
Arthur Abnous - Irvine CA
Henry Samueli - San Juan Capistrano CA

Broadcom Corporation - Irvine CA

H04L 700

375371, 370516

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals.

6472940, Oct 29, 2002

Nov 13, 2000

09/712422

Arya R. Behzad - Danville CA
Klaas Bult - Boschen Duin, NL
Ramon A. Gomez - Fountain Valley CA
Chi-Hung Lin - Mission Viejo CA
Tom W. Kwan - Cupertino CA
Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Bunnik, NL
Arthur Abnous - Irvine CA
Henry Samueli - Corona del Mar CA

Broadcom Corporation - Irvine CA

G03G 310

330279, 330144

Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductors switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

6477200, Nov 5, 2002

Nov 9, 1999

09/437719

Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Utrecht, NL
Arthur Abnous - Irvine CA
Henry Samueli - San Juan Capistrano CA

Broadcom Corporation - Irvine CA

H03H 730

375233, 375285

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals.

6707848, Mar 16, 2004

Nov 30, 2000

09/726642

Oscar E. Agazzi - Irvine CA
David Kruse - Utrecht, NL
Arthur Abnous - Irvine CA
Mehdi Hatamian - Mission Viejo CA

Broadcom Corporation - Irvine CA

H03K 5159

375229

A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and, a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.

6721916, Apr 13, 2004

May 15, 2001

09/858990

Oscar E. Agazzi - Irvine CA
David Kruse - Newport Beach CA
Arthur Abnous - Irvine CA
Mehdi Hatamian - Mission Viejo CA

Broadcom Corporation - Irvine CA

H03M 1303

714752, 375262, 375265, 375341, 714794, 714795

A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in a set of symbols. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

6731691, May 4, 2004

Jul 26, 2002

10/205735

Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
Henry Samueli - San Juan Capistrano CA
David E. Kruse - Utrecht, NL
Arthur Abnous - Irvine CA

Broadcom Corp. - Irvine CA

H09B 1500

375285, 375224

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals.

6771725, Aug 3, 2004

Jul 29, 2002

10/207305

Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Utrecht, NL
Arthur Abnous - Irvine CA
Henry Samueli - San Juan Capistrano CA

Broadcom Corporation - Irvine CA

H04L 700

375355, 375371, 331 2, 331 46

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals.