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Aron T Lunde

from Boise, ID
Age ~54
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Also known as:
Aron Tucker Lunde, Aron Lunde Tucker
Phone and address:
2226 E Skipperling Ln, Boise, ID 83706
(208) 867-5649
Related to:
Nayne Lunde Ro, 78Terry Lunde, 35Michael Debenedetti, 62Colette Debenedetti, 60Al Lunde, 66
Connected to:
Alexander S Lunde, 28Brenda L Lunde, 76Brent W Lunde, 40Cari L Lunde, 58Carrie Lunde, 71Chelsea A Lunde, 38Ethan Lunde, 32Fred R Lunde, 78Fred M Lunde, 60Garrett Lunde, 33

Aron Lunde Phones & Addresses

  • 2226 E Skipperling Ln, Boise, ID 83706 (208) 867-5649 (208) 384-0157
  • 5503 E Stageline Dr, Boise, ID 83716
  • 870 W Belmont St #203, Boise, ID 83706 (208) 582-8694
  • Mountain Home, ID
  • 2008 S Fruitland St, Kennewick, WA 99337 (509) 582-8694
  • Cottonwood Heights, UT
  • 7649 Brighton Way, Salt Lake City, UT 84121
  • Oro Valley, AZ

Resumes

Resumes

Aron Lunde Photo 1

Senior Manager, Corporate Strategy

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology Jan 2009 - Feb 2015
Program Manager, Hybrid Memory Cube
Micron Technology Jan 2009 - Feb 2015
Senior Manager, Corporate Strategy
Micron Technology Jun 2001 - Jan 2009
Designer, Dram
Micron Technology Jun 1, 1994 - Jun 1, 2001
Test Engineer
Education:
University of Idaho 1989 - 1994
Bachelors, Bachelor of Science, Electrical Engineering Boise State University 1975 - 1976
Master of Business Administration, Masters
Skills:
Semiconductors
Product Engineering
Training
Engineering Management
Architecture
Testing
Ic
Mobile Devices
Soc
Asic
Cmos
Electronics
Semiconductor Industry
Product Management
Cross Functional Team Leadership
Manufacturing
Product Marketing
Debugging
Product Development
Strategic Planning
Program Management
Strategy
Leadership
Interests:
Rugby
Youth Soccer Coach
Snake River Rugby Club
Triathlons
2006 Ironman Canada Finisher
2016 Ironman Coeurd'alene Finisher
1996 Division Ii Rugby National Champion
Aron Lunde Photo 2

Aron Lunde

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Location:
Boise, ID
Aron Lunde Photo 3

Program Manager At Micron Technology Inc.

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Position:
Program Manager at Micron Technology Inc.
Location:
Boise, Idaho Area
Industry:
Semiconductors
Work:
Micron Technology Inc. since 2010
Program Manager
Micron Technology Jun 2001 - Jan 2009
Designer
Micron Technology Jun 1994 - Jun 2001
Test Engineer
Education:
University of Idaho 1989 - 1994
BS, Electrical Engineering
Skills:
Testing
Mobile Devices
Training
Semiconductors
Architecture
IC
ASIC
SoC
CMOS
Engineering Management
Product Engineering
Analog
Aron Lunde Photo 4

Engineer At Micron Technology

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Position:
Engineer at Micron Technology
Location:
Boise, Idaho Area
Industry:
Computer Hardware
Work:
Micron Technology
Engineer
Aron Lunde Photo 5

Aron Lunde

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Location:
Boise, Idaho Area
Industry:
Semiconductors

Publications

Us Patents

Method And Apparatus For Properly Disabling High Current Parts In A Parallel Test Environment

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US Patent:
6522161, Feb 18, 2003
Filed:
Jul 5, 2001
Appl. No.:
09/898047
Inventors:
Aron T. Lunde - Boise ID
Phillip A. Rasmussen - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01R 3126
US Classification:
324765, 3241581
Abstract:
A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i. e. , the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.

Probe Look Ahead: Testing Parts Not Currently Under A Probehead

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US Patent:
6630685, Oct 7, 2003
Filed:
Jun 24, 2002
Appl. No.:
10/178111
Inventors:
Aron T. Lunde - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2358
US Classification:
257 48, 257691, 438 14
Abstract:
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i. e.

Signal Sharing Circuit With Microelectric Die Isolation Features

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US Patent:
6967348, Nov 22, 2005
Filed:
Jun 20, 2002
Appl. No.:
10/176330
Inventors:
Timothy B. Cowles - Boise ID, US
Aron T. Lunde - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L023/58
H01L021/66
G06F017/50
US Classification:
257 48, 257 68, 257 71, 257238, 257905, 257906, 257908, 438 17, 438239, 438244, 438250, 438253, 716 18
Abstract:
A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal.

Isolation Circuit

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US Patent:
7026646, Apr 11, 2006
Filed:
Jun 20, 2002
Appl. No.:
10/176015
Inventors:
Timothy B. Cowles - Boise ID, US
Aron T. Lunde - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 23/58
US Classification:
257 48, 257786, 257620, 257203, 257678, 257692, 438 18, 438462
Abstract:
An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Probe Look Ahead: Testing Parts Not Currently Under A Probehead

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US Patent:
7122829, Oct 17, 2006
Filed:
Sep 3, 2003
Appl. No.:
10/654655
Inventors:
Aron T. Lunde - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 23/58
US Classification:
257 48, 257723, 438 14, 438 15
Abstract:
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i. e.

Probe Look Ahead: Testing Parts Not Currently Under A Probehead

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US Patent:
7170091, Jan 30, 2007
Filed:
Jan 12, 2006
Appl. No.:
11/330810
Inventors:
Aron T Lunde - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 23/58
US Classification:
257 48, 257723
Abstract:
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i. e.

Dynamic Integrated Circuit Clusters, Modules Including Same And Methods Of Fabricating

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US Patent:
7208758, Apr 24, 2007
Filed:
Sep 16, 2003
Appl. No.:
10/663898
Inventors:
Aron T. Lunde - Boise ID, US
Kevin G. Duesman - Boise ID, US
Timothy B. Cowles - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 23/58
US Classification:
257 48, 257723, 257778
Abstract:
A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The wafer is subjected to testing to identify functional and nonfunctional dice. The locations of the functional dice are analyzed to determine the location of immediately adjacent or closely proximate functional dice. A group of functional dice is identified and an interconnection circuit is formed therebetween. The functional die group, once interconnected, is then segmented from the wafer while maintaining the unitary integrity of the functional die group as well as the associated interconnections between dice. Modules including one or more functional die groups and methods of fabricating functional die groups and modules are also disclosed.

Combination Column Redundancy System For A Memory Array

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US Patent:
7251173, Jul 31, 2007
Filed:
Aug 2, 2005
Appl. No.:
11/195878
Inventors:
Aron Lunde - Boise ID, US
Michael Shore - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
US Classification:
365200, 36523003, 36523006
Abstract:
A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.
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Aron T Lunde from Boise, ID, age ~54 Get Report