Resumes
Resumes
Arnold Schnell Phones & Addresses
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Hutto, TX
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Elgin, TX
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Round Rock, TX
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100 Hall St, Pflugerville, TX 78660 (512) 251-7814
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Garland, TX
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Longview, TX
Work
Position:
Craftsman/Blue Collar
Education
Degree:
Associate degree or higher
Emails
Publications
Us Patents
Power Supply Shutdown Control
View pageUS Patent:
6903583, Jun 7, 2005
Filed:
Jan 30, 2004
Appl. No.:
10/768642
Inventors:
Ahsan Habib - Pflugerville TX, US
Arnold T. Schnell - Pflugerville TX, US
Arnold T. Schnell - Pflugerville TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
H03L007/00
US Classification:
327143, 327198
Abstract:
When a power supply is turned off its output voltages decrease over certain times. If the power supply is turned back on before the output voltages have had time to decrease to a level required by certain electronic circuits before power is reapplied, then these electronic circuits may malfunction or latch-up. A power supply shutdown control monitors voltage levels of the power supply. The power supply shutdown control prevents the power supply from being turned back on before the output voltages have reached a sufficiently low voltage level. A voltage reset monitor determines when a power supply voltage drops below a certain level, and then a memory device stores the instance of a power supply voltage drop and uses the stored instance to prevent the power supply from being turned on until the monitored voltage(s) have reached the sufficiently low voltage level. Then, the stored instance is reset and the power supply may be re-energized.
Embedded Control And Monitoring Of Hard Disk Drives In An Information Handling System
View pageUS Patent:
6957288, Oct 18, 2005
Filed:
Feb 19, 2003
Appl. No.:
10/368764
Inventors:
Joyce Metevier - Round Rock TX, US
Ahsan Habib - Pflugerville TX, US
Arnold T. Schnell - Pflugerville TX, US
Ahsan Habib - Pflugerville TX, US
Arnold T. Schnell - Pflugerville TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F013/00
US Classification:
710100, 710301, 710302, 710305, 710306
Abstract:
The need for a SAF-TE processor embedded on a SCSI backplane of a hot-swap hard disk drive enclosure is eliminated by utilizing the functionality of a RAID on motherboard (ROMB) controller and an Embedded Server Management (ESM) interface already present in an information handling system. Only sensors and input-output (I/O) registers remain on the SCSI backplane as required. The SCSI backplane I/O is split between the ESM and ROMB according to functional requirements.
System And Method For Flexible Storage And Networking Provisioning In Large Scalable Processor Installations
View pageUS Patent:
20130107444, May 2, 2013
Filed:
Oct 28, 2011
Appl. No.:
13/284855
Inventors:
Arnold Thomas Schnell - Pflugerville TX, US
Richard Owen Waldorf - Austin TX, US
David Borland - Austin TX, US
Richard Owen Waldorf - Austin TX, US
David Borland - Austin TX, US
Assignee:
Calxeda, Inc. - Austin TX
International Classification:
G06F 1/18
H05K 13/00
G06F 1/20
H05K 13/00
G06F 1/20
US Classification:
36167933, 36167931, 295921
Abstract:
A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.
Node Cards For A System And Method For Modular Compute Provisioning In Large Scalable Processor Installations
View pageUS Patent:
20130111229, May 2, 2013
Filed:
Jun 19, 2012
Appl. No.:
13/527498
Inventors:
David Borland - Austin TX, US
Arnold Thomas Schnell - Pflugerville TX, US
Mark Davis - Austin TX, US
Arnold Thomas Schnell - Pflugerville TX, US
Mark Davis - Austin TX, US
Assignee:
Calxeda, Inc. - Austin TX
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be used.
System Board For System And Method For Modular Compute Provisioning In Large Scalable Processor Installations
View pageUS Patent:
20130111230, May 2, 2013
Filed:
Jun 19, 2012
Appl. No.:
13/527505
Inventors:
David Borland - Austin TX, US
Arnold Thomas Schnell - Pflugerville TX, US
Mark Davis - Austin TX, US
Arnold Thomas Schnell - Pflugerville TX, US
Mark Davis - Austin TX, US
Assignee:
Calxeda, Inc. - Austin TX
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
A system for a system and method for provisioning of modular compute resources within a system design are provided.
System And Method For Preservation Of Battery Power During Reconditioning
View pageUS Patent:
62395785, May 29, 2001
Filed:
Jun 27, 2000
Appl. No.:
9/604242
Inventors:
Arnold Thomas Schnell - Pflugerville TX
Shawn Joel Dube - Austin TX
Shawn Joel Dube - Austin TX
Assignee:
Dell Products, L.P., a Texas Limited Partnership - Round Rock TX
International Classification:
H02J 700
US Classification:
320119
Abstract:
A battery reconditioning circuit for a computer system is disclosed. The battery reconditioning circuit comprises a battery charger, a battery reconditioner and at least two sets of batteries. While one set of batteries is being reconditioned by the battery charger and the battery reconditioner, at least one set of batteries remains connected to the load. Therefore, even if the computer system suffers power loss while one set of batteries is being reconditioned, there is at least one battery available to provide backup power.
Method And Apparatus For Hashing Addresses In A Network Switch
View pageUS Patent:
57577951, May 26, 1998
Filed:
May 20, 1996
Appl. No.:
8/650456
Inventors:
Arnold Thomas Schnell - Pflugerville TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
H04N 1256
US Classification:
370392
Abstract:
A hash system for selecting a destination network port for each of a plurality of binary address values, such as media access control (MAC) addresses, received by a plurality of network ports including a hash memory for receiving binary hash values and for providing a corresponding port number identifying a destination network port. Each of the network ports includes hash logic for receiving a binary address value, for selecting a subset of bits of each received binary address value as a binary hash value, for providing the binary hash value to the hash memory and for receiving a corresponding port number. The subset of bits are determined by a bit enable value. The hash system further includes processor logic for sorting the binary address values among the network ports, for determining and periodically updating the bit enable value to optimize uniqueness of correspondingly updated binary hash values corresponding to the binary address values, for providing updated bit enable values to the hash logic of each of the plurality of network ports and for programming the hash memory according to the updated binary hash values. The processor periodically performs a single-bit comparison and a double-bit comparison for updating the bit enable value.
Management Communication Bus For Networking Devices
View pageUS Patent:
61991333, Mar 6, 2001
Filed:
Mar 29, 1996
Appl. No.:
8/624176
Inventors:
Arnold Thomas Schnell - Pflugerville TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300
US Classification:
710110
Abstract:
A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.