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Arnold E Baizley

from Richmond, VT
Age ~63
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Also known as:
Anrold Baizley
Related to:
Alice B BakerGlenn A Cutlip, 68
Connected to:
Theodore J Baj, 102Joycelyn M Baja, 69Romeo M Baja, 79Bernadette B Bajacan, 48Craig S Bajadali, 63Elizabeth D Bajadek, 36Ambar V Bajaj, 39Avneet Bajaj, 44Bhavana Bajaj, 38Gitanjali Bajaj, 44

Arnold Baizley Phones & Addresses

  • Richmond, VT
  • 623 Pleasant Valley Rd, Underhill, VT 05489 (802) 899-3281
  • Essex Junction, VT
  • Cambridge, VT
  • 623 Pleasant Valley Rd, Underhill, VT 05489

Publications

Us Patents

Detection Method For Identifying Unintentionally Forward-Biased Diode Devices In An Integrated Circuit Device Design

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US Patent:
7685548, Mar 23, 2010
Filed:
Sep 27, 2007
Appl. No.:
11/862887
Inventors:
Arnold E. Baizley - Underhill VT, US
Joseph A. Iadanza - Hinesburg VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 2
Abstract:
A detection method for identifying unintentionally forward-biased diode devices identifies one or more forward-biased diodes directly from a graphical representation of an integrated circuit (IC) device design. The graphical representation describing one or more IC components as a plurality of geometric shapes that correspond to a set of patterns in at least one semiconductor layer. A detection method may work in conjunction with one or more checks (e. g. , electrical rule check (ERC)) to analyze the graphical representation and ensure its manufacturability by reducing the likelihood the forward-biased diodes will be present in the manufactured IC device.

Esd Power Clamp In Triple Well

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US Patent:
20080029824, Feb 7, 2008
Filed:
Aug 2, 2006
Appl. No.:
11/461831
Inventors:
Arnold E. Baizley - Underhill VT, US
Philippe Hauviller - Itteville, FR
Steven H. Voldman - South Burlington VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 29/76
US Classification:
257371
Abstract:
A power clamp in a triple well is disclosed. A metal oxide semiconductor (MOS) varactor is used in a triggering circuit and is positioned in a first N type well. An N-channel field effect transistor is positioned in a P-type well. A P-channel field effect transistor is positioned in a second N-type well. The first N-type well is electrically isolated from the second N-type well, and electrically contacts the substrate of the power clamp.

Virtual Voltage Power Supply

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US Patent:
60114231, Jan 4, 2000
Filed:
May 23, 1997
Appl. No.:
8/862896
Inventors:
Arnold E. Baizley - Underhill VT
Anthony R. Bonaccio - Shelburne VT
Charles J. Masenas - Essex Junction VT
Steven J. Tanghe - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 1756
US Classification:
327423
Abstract:
A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.

Transition Detector With Timer

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US Patent:
59072504, May 25, 1999
Filed:
May 16, 1997
Appl. No.:
8/857259
Inventors:
Arnold E. Baizley - Cambridge VT
Steven J. Tanghe - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 51534
US Classification:
327 18
Abstract:
A circuit for detecting delay of more than a set period of time from a last signal transition for any of a plurality of data signals, comprising a differential comparator, and integrator pairs for each signal, one integrator of the pair being triggered by transition of the signal from low to high and the other triggered by transition of the inverse of the signal from low to high, each integrator having a voltage measured by the differential comparator against a reference voltage, each integrator being reset by the trigger for the other integrator.

Integrated Circuit Performance Modeling Using A Connectivity-Based Condensed Resistance Model For A Conductive Structure In An Integrated Circuit

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US Patent:
20160140273, May 19, 2016
Filed:
Nov 18, 2014
Appl. No.:
14/546065
Inventors:
- Armonk NY, US
Arnold E. Baizley - Underhill VT, US
Ning Lu - Essex Junction VT, US
Judith H. McCullen - Essex Junction VT, US
Cole E. Zemke - Essex Junction VT, US
International Classification:
G06F 17/50
Abstract:
Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.
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Arnold E Baizley from Richmond, VT, age ~63 Get Report