Arne S Barras

7380219, May 27, 2008

Feb 10, 2005

11/054862

Arne S. Barras - Longmont CO, US
Rajeev Jayaraman - Saratoga CA, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716 1, 716 16, 716 18

Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed () with at least one design tool. Statistical data is captured () for the at least one design tool and operational attributes thereof are automatically adjusted () in response to the statistical data. A second version of the circuit design is processed () with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed () with at least one design tool in a first iteration. Statistical data is captured () for the at least one design tool and operational attributes thereof are automatically adjusted () for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed () with the at least one design tool having the adjusted operational attributes in the second iteration.

7979816, Jul 12, 2011

Apr 9, 2008

12/100313

Arne S. Barras - Longmont CO, US
Rajeev Jayaraman - Saratoga CA, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716102, 716106, 716110, 716119, 716122, 716123

Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed () with at least one design tool. Statistical data is captured () for the at least one design tool and operational attributes thereof are automatically adjusted () in response to the statistical data. A second version of the circuit design is processed () with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed () with at least one design tool in a first iteration. Statistical data is captured () for the at least one design tool and operational attributes thereof are automatically adjusted () for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed () with the at least one design tool having the adjusted operational attributes in the second iteration.

7086029, Aug 1, 2006

Feb 18, 2003

10/370329

Arne S. Barras - Longmont CO, US
Jeffrey M. Mason - Eldorado Springs CO, US
Kate L. Kelley - Longmont CO, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716 17, 716 5

Method and apparatus for incremental design is described. More particularly, a text-circuit description of the integrated circuit having logic groups of respective logic instances is obtained. Area groups are created for the logic groups and correspondingly assigned. Unchanged logic groups are guided on an incremental implementation from existing guide files, and changed logic groups are re-implemented in area groups corresponding to the changed logic groups. In this manner, runtime of the unchanged logic groups is reduced by an incremental guide implementation instead of a re-implementation, while performance of such unchanged logic groups is maintained from a prior implementation. Furthermore, degrees of freedom for re-implementing are enhanced for improving a design, as all prior mapping, placing and routing within a changed area group may be stripped for re-implementation.