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Arnab Raha

from San Jose, CA
Age ~35
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Connected to:
Ranjan Raha, 58Gillian P Rahael, 46Delcie Rahaim, 77Donna M Rahaim, 69John P Rahaim, 72Collin Rahal, 39Elaine B Rahal, 56Elias A Rahal, 45Kalina R Rahal, 50Lawrence E Rahal, 94

Arnab Raha Phones & Addresses

  • San Jose, CA
  • West Lafayette, IN
  • W Lafayette, IN

Work

Company: Intel labs Sep 2017 to May 2019 Position: Research scientist

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Purdue University 2012 to 2016 Specialities: Computer Engineering, Electronics, Electronics Engineering, Philosophy

Skills

C • Embedded Systems • C++ • Algorithms • Simulations • Vhdl • Latex • Java • Programming • Signal Processing • Microsoft Excel • Research • Data Structures • Verilog • Tinyos • Powerpoint • Soc • Operating Systems • Matlab • Electronic System Design • Chisel

Interests

Economic Empowerment • Education • Environment • Science and Technology • Health

Industries

Research

Resumes

Resumes

Arnab Raha Photo 1

Research Scientist

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Location:
Santa Clara, CA
Industry:
Research
Work:
Intel Labs Sep 2017 - May 2019
Research Scientist
Movidius Sep 2017 - May 2019
Research Scientist
Purdue University Aug 2012 - Aug 2017
Bilsland Fellow and Research Assistant at Embedded Systems Laboratory, Purdue University
Intel Labs May 2014 - Sep 2014
Research Intern
Jadavpur University Jul 2008 - Jun 2012
Bachelor of Electronics and Telecommunication Engineering
Education:
Purdue University 2012 - 2016
Doctorates, Doctor of Philosophy, Computer Engineering, Electronics, Electronics Engineering, Philosophy Jadavpur University 2008 - 2012
Bachelor of Engineering, Bachelors, Engineering, Electronics South Point High School, Kolkata 1993 - 2008
Higher Secondary School 2008
South Point High School 1993 - 2008
South Point High School 2006
Jadavpur University
Bachelors, Bachelor of Arts Purdue University
Skills:
C
Embedded Systems
C++
Algorithms
Simulations
Vhdl
Latex
Java
Programming
Signal Processing
Microsoft Excel
Research
Data Structures
Verilog
Tinyos
Powerpoint
Soc
Operating Systems
Matlab
Electronic System Design
Chisel
Interests:
Economic Empowerment
Education
Environment
Science and Technology
Health

Publications

Us Patents

Data Reuse In Deep Learning

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US Patent:
20220188638, Jun 16, 2022
Filed:
Mar 2, 2022
Appl. No.:
17/684764
Inventors:
- Santa Clara CA, US
Arnab Raha - Santa Clara CA, US
Raymond Jit-Hung Sung - San Francisco CA, US
Debabrata Mohapatra - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/08
G06N 3/063
G06F 7/544
Abstract:
An apparatus for convolution operations is provided. The apparatus includes a PE array, a datastore, writing modules, reading modules, and a controlling module. The PE array performs MAC operations. The datastore includes databanks, each of which stores data to be used by a column of the PE array. The writing modules transfer data from a memory to the datastore. The reading modules transfer data from the datastore to the PE array. Each reading module may transfer data to a particular column of the PE array. The controlling module can determine the rounds of a convolution operation. Each round includes MAC operations based on a weight. The controlling module controls the writing modules and reading modules so that the same data in a databank can be reused in multiple rounds. For different rounds, the controlling module can provide a reading module accesses to different databanks.

Accelerating Data Load And Computation In Frontend Convolutional Layer

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US Patent:
20230073661, Mar 9, 2023
Filed:
Nov 14, 2022
Appl. No.:
18/055315
Inventors:
- Santa Clara CA, US
Arnab Raha - San Jose CA, US
Umer Iftikhar Cheema - Hillsboro OR, US
Raymond Jit-Hung Sung - San Francisco CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/04
G06F 17/16
G06N 3/08
Abstract:
An DNN (deep neural network) accelerator may accelerate deep learning, such as convolutions in frontend layers through a scheduler for loading data to be processed. The DNN accelerator may store, in a memory, an input tensor of a convolutional layer in a DNN. The convolutional layer may be the first layer or a layer that is arranged before the one or more other convolutional layers in the DNN such that data processed by the first layer can be efficiently reused across data load rounds. The input tensor includes one or more channels. A channel includes activations arranged in rows and columns. The DNN accelerator may read at least a portion of the input tensor from the memory into a datastore. The datastore includes some databanks. The DNN accelerator may provide a vector of one or more activations to a processing element for operations such as multiplications on the vector.

Deep Neural Network (Dnn) Accelerator Facilitating Quantized Inference

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US Patent:
20230059976, Feb 23, 2023
Filed:
Oct 18, 2022
Appl. No.:
18/047415
Inventors:
- Santa Clara CA, US
Arnab Raha - San Jose CA, US
Raymond Jit-Hung Sung - San Francisco CA, US
Martin Power - Dublin, IE
Umer Iftikhar Cheema - Hillsboro OR, US
David Thomas Bernard - Kilcullen, IE
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/08
Abstract:
An DNN accelerator may include a PE array performing MAC operations. The PE array may include PEs capable of MAC operations on quantized values. A PE may include subtractors for subtracting zeropoints from quantized activations and quantized weights to generate intermediate activations and intermediate weights. The intermediate activations and intermediate weights may be stored in data storage units in the PE and maybe used by an MAC unit in the PE. The subtractors may be placed outside the MAC unit but inside the PE. The MAC unit may perform sequential cycles of MAC operations. The MAC unit may include a plurality of multipliers. The intermediate activations and intermediate weights stored in the data storage units may be reused by different multipliers in different cycles of MAC operations. An output of the MAC unit or of the PE may be multiplied with a quantization scale to produce a floating-point value.

Techniques For Increasing Activation Sparsity In Artificial Neural Networks

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US Patent:
20230021396, Jan 26, 2023
Filed:
Sep 27, 2022
Appl. No.:
17/953637
Inventors:
- Santa Clara CA, US
Arnab Raha - San Jose CA, US
Bogdan Pasca - Toulouse, FR
Martin Langhammer - Salisbury, GB
Michael Wu - Belmont CA, US
Deepak Mathaikutty - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/04
G06N 3/08
Abstract:
A method for implementing an artificial neural network in a computing system that comprises performing a compute operation using an input activation and a weight to generate an output activation, and modifying the output activation using a noise value to increase activation sparsity.

Power Efficient Register Files For Deep Neural Network (Dnn) Accelerator

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US Patent:
20230014656, Jan 19, 2023
Filed:
Sep 23, 2022
Appl. No.:
17/934665
Inventors:
Raymond Jit-Hung Sung - San Francisco CA, US
Deepak Abraham Mathaikutty - Chandler AZ, US
Amit Agarwal - Hillsboro OR, US
David Thomas Bernard - Kilcullen, IE
Steven Hsu - Lake Oswego OR, US
Martin Power - Dublin, IE
Conor Byme - Dublin, IE
Arnab Raha - San Jose CA, US
International Classification:
G01R 31/3177
G06N 3/04
Abstract:
A memory array of a compute tile may store activations or weights of a DNN. The memory array may include databanks for storing contexts, context MUXs, and byte MUXs. A databank may store a context with flip-flop arrays, each of which includes a sequence of flip-flops. A logic gate and an ICG unit may gate flip-flops and control whether states of the flip-flops can be changed. The data gating can prevent a context not selected for the databank from inadvertently toggling and wasting power A context MUX may read a context from different flip-flop arrays in a databank based on gray-coded addresses. A byte MUX can combine bits from different bytes in a context read by the context MUX. The memory array may be implemented with bit packing to reduce distance between the context MUX and byte MUX to reduce lengths of wires connecting the context MUXs and byte MUXs.

Deep Neural Network (Dnn) Accelerators With Weight Layout Rearrangement

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US Patent:
20230017662, Jan 19, 2023
Filed:
Sep 16, 2022
Appl. No.:
17/946231
Inventors:
Sudheendra Kadri - Folsom CA, US
Darren Crews - Portland OR, US
Deepak Abraham Mathaikutty - Chandler AZ, US
Andrea Deidda - Celbridge, IE
Arnab Raha - San Jose CA, US
Kevin Brady - Newry, GB
David Thomas Bernard - Kilcullen, IE
International Classification:
G06N 3/063
G06F 13/28
Abstract:
An DNN accelerator includes a DMA engine that can rearrange weight data layout. The DMA engine may read a weight tensor from a memory (e.g., DRAM). The weight tensor includes weights arranged in a 3D matrix. The DMA engine may partition the weight tensor into a plurality of virtual banks based on a structure of a PE array, e.g., based on the number of activated PE columns in the PE array. Then the DMA engine may partition a virtual bank into a plurality of virtual sub-banks. The DMA engine may also identify data blocks from different ones of the plurality of virtual sub-banks. A data block may include a plurality of input channels and may have a predetermined spatial size and storage size. The DMA engine form a linear data structure by interleaving the data blocks. The DMA engine can write the linear data structure into another memory (e.g., SRAM).

Sparsity Processing On Unpacked Data

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US Patent:
20230018857, Jan 19, 2023
Filed:
Sep 19, 2022
Appl. No.:
17/947642
Inventors:
Martin Power - Dublin, IE
Conor Byrne - Dublin, IE
Niall Hanrahan - Galway, IE
Deepak Abraham Mathaikutty - Chandler AZ, US
Arnab Raha - San Jose CA, US
Raymond Jit-Hung Sung - San Francisco CA, US
David Thomas Bernard - Kilcullen, IE
Kevin Brady - Newry, GB
Martin-Thomas Grymel - Leixlip, IE
International Classification:
G06N 3/04
G06N 3/08
Abstract:
Sparsity processing within a compute block can be done on unpacked data. The compute block includes a sparsity decoder that generates a combined sparsity vector from an activation sparsity vector and a weight sparsity vector. The activation sparsity vector indicates positions of non-zero valued activations in an activation context. The weight sparsity vector indicates positions of non-zero valued weights in a weight context. The combined sparsity vector comprises one or more zero valued bits and one or more non-zero valued bits. The sparsity decoder may determine the position of a non-zero valued bit in the combined sparsity vector and determine an address for the non-zero valued activation and the non-zero valued weight based on the position of the non-zero valued bit. The non-zero valued activation and the non-zero valued weight may be provided to a PE for performing MAC operations.

Performance Scaling For Dataflow Deep Neural Network Hardware Accelerators

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US Patent:
20210271960, Sep 2, 2021
Filed:
Apr 30, 2021
Appl. No.:
17/246341
Inventors:
Arnab Raha - Santa Clara CA, US
Debabrata Mohapatra - Santa Clara CA, US
Gautham Chinya - Sunnyvale CA, US
Guruguhanathan Venkataramanan - Livermore CA, US
Sang Kyun Kim - San Jose CA, US
Deepak Mathaikutty - Santa Clara CA, US
Raymond Sung - San Francisco CA, US
Cormac Brick - San Francisco CA, US
International Classification:
G06N 3/063
G06N 3/04
Abstract:
Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.
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Arnab Raha from San Jose, CA, age ~35 Get Report