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Arjun Pradeep

from Milpitas, CA
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Also known as:
Pradeep Arjun
Related to:
Pradeep Arjun
Connected to:
Meera Pradeep, 52Praveen Pradeep, 37Sudha Pradeep, 54David Pradel, 93Eduardo A Pradel, 48Ken Pradel, 36Laurent O Pradel, 29Monica A Pradel, 36Robin B Pradel, 70Thomas F Pradel, 78

Arjun Pradeep Phones & Addresses

  • Milpitas, CA
  • Santa Clara, CA
  • Hillsboro, OR

Work

Company: Intel corporation Jul 2015 Position: Soc design engineer

Education

Degree: Masters School / High School: University of Cincinnati 2014 to 2015 Specialities: Computer Engineering

Skills

Atpg • Verilog • Jtag • Mbist • Static Timing Analysis • Perl • Fpga • Gls • Bist • Dft Compiler • Simvision • Unix • Scan Insertion • Tetramax • Mentor Tessent • Synplify Pro • Altera Quartus • Bscan • Vhdl • Vlsi • C++ • Ncsim • C • Awk • Sed • Asic • Soc • Rtl Design • Testing • Matlab • Dft • Linux • Design For Manufacturing • Memory Test • Silicon Validation • Front End Design • Logic Synthesis • Timing Closure • Lec • Ijtag • Emulation • Ovm • System Verilog • Eda • Boundary Scan • Gate Level Simulation • Assertions • Assertion Based Verification • Open Verification Methodology

Languages

English • Malayalam • Hindi • Tamil

Interests

Economic Empowerment • Education • Environment • Science and Technology • Human Rights • Health

Industries

Semiconductors

Resumes

Resumes

Arjun Pradeep Photo 1

Soc Design Engineer

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Location:
630 Park View Dr, Santa Clara, CA 95054
Industry:
Semiconductors
Work:
Intel Corporation
Soc Design Engineer
Wipro Technologies Jul 2011 - Jul 2014
Dft Project Engineer
Education:
University of Cincinnati 2014 - 2015
Masters, Computer Engineering College of Engineering, Trivandrum 2007 - 2011
Bachelors, Communication, Electronics Nirmala Matha Central School, Thrissur 2005 - 2007
Sree Sankara Vidya Peetam 1995 - 2005
Skills:
Atpg
Verilog
Jtag
Mbist
Static Timing Analysis
Perl
Fpga
Gls
Bist
Dft Compiler
Simvision
Unix
Scan Insertion
Tetramax
Mentor Tessent
Synplify Pro
Altera Quartus
Bscan
Vhdl
Vlsi
C++
Ncsim
C
Awk
Sed
Asic
Soc
Rtl Design
Testing
Matlab
Dft
Linux
Design For Manufacturing
Memory Test
Silicon Validation
Front End Design
Logic Synthesis
Timing Closure
Lec
Ijtag
Emulation
Ovm
System Verilog
Eda
Boundary Scan
Gate Level Simulation
Assertions
Assertion Based Verification
Open Verification Methodology
Interests:
Economic Empowerment
Education
Environment
Science and Technology
Human Rights
Health
Languages:
English
Malayalam
Hindi
Tamil
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Arjun Pradeep from Milpitas, CA Get Report