Archibald J Allen

6335272, Jan 1, 2002

Aug 14, 2000

09/637935

Archibald Allen - Shelburne VT
Jerome B. Lasky - Essex Junction VT
Randy W. Mann - Jericho VT
Jed H. Rankin - Burlington VT
Francis R. White - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 214763

438621, 438620, 257773, 257372

A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

6429469, Aug 6, 2002

Nov 2, 2000

09/705031

Archibald J. Allen - Grand Isle VT
Orest Bula - Shelburne VT
John M. Cohn - Richmond VT
Daniel Cole - Jericho VT
Edward W. Conrad - Jeffersonville VT
William C. Leipold - Enosburg Falls VT

International Business Machines Corporation - Armonk NY

H01L 2710

257207, 257202

A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.

6738954, May 18, 2004

Aug 10, 2000

09/636478

Archibald J. Allen - Grand Isle VT
Wilm E. Donath - New York NY
Alan D. Dziedzic - Newburgh NY
Mark A. Lavin - Katonah NY
Daniel N. Maynard - Craftsbury Common VT
Dennis M. Newns - Yorktown Heights NY
Gustavo E. Tellez - Essex Junction VT

International Business Machines Corporation - Armonk NY

G06F 1750

716 4, 716 1

A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

61401714, Oct 31, 2000

Jan 20, 1999

9/233549

Archibald John Allen - Shelburne VT
Jerome Brett Lasky - Essex Junction VT
Randy William Mann - Jericho VT
John Joseph Pekarik - Underhill VT
Jed Hickory Rankin - Burlington VT
Edward William Sengle - Hinesburg VT
Francis Roger White - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 21336

438230

A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.

6038168, Mar 14, 2000

Jun 26, 1998

9/105339

Archibald J. Allen - Shelburne VT
Jerome B. Lasky - Essex Junction VT
John J. Pekarik - Underhill VT
Jed H. Rankin - Burlington VT
Francis R. White - Essex Junction VT

International Business Machines Corporation - Armonk NY

G11C 700

36518507

A method and apparatus for conditioning an integrated circuit to always enter a desired operating state when actuated by permanently altering at least one component device. An integrated circuit is provided with at least one component transistor wherein a constant high voltage is applied only once to the drain electrode of the transistor for one predetermined period of time while concurrently a constant voltage lower than the high voltage is applied only once to the gate electrode of the transistor, thus causing a permanent channel hot-electron alteration of a gate oxide of the transistor. The integrated circuit may include a plurality of programmable circuits, each capable of assuming a plurality of readable data states when powered up, and each including a plurality of programmable devices for permanently biasing its corresponding programmable circuit to assume one of the readable states upon subsequent power ups.

60906731, Jul 18, 2000

Oct 20, 1998

9/175304

Archibald J. Allen - Shelburne VT
Toshiharu Furukawa - Essex Junction VT
Edward F. O'Neil - Essex Junction VT
Mark C. Hakey - Milton VT
Roger A. Verhelst - Colchester VT
David V. Horak - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 21336
H01L 213205

438301

The present invention overcomes the difficulties found in the background art by providing a direct low resistive contact between devices on a semiconductor chip without excessive current leakage. Current leakage is prevented in the preferred design by using silicon on insulator (SOI) construction for the chip. By constructing the direct contact over an insulator, such as silicon dioxide, current leakage is minimized. The preferred embodiment uses silicide to connect a polysilicon gate to a doped region of the substrate. An alternative embodiment of the present invention provides for the use of conductive studs to electrically connect devices. An increased density of approximately twenty percent may be realized using the present invention.

62478532, Jun 19, 2001

May 26, 1998

9/085093

Evanthia Papadopoulou - Elmsford NY
Mark Alan Lavin - Katonah NY
Gustavo Enrique Tellez - Cornwall on Hudson NY
Archibald John Allen - Shelburne VT

International Business Machines Corporation - Armonk NY

G06F 1750

39550005

An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the L. sub. infin. or the L. sub. 1 metric instead of the Euclidean geometry.

61539341, Nov 28, 2000

Jul 30, 1998

9/126577

Archibald Allen - Shelburne VT
Jerome B. Lasky - Essex Junction VT
Randy W. Mann - Jericho VT
Jed H. Rankin - Burlington VT
Francis R. White - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 2348

257773

A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.