Anurag Jindal

20120244705, Sep 27, 2012

Mar 23, 2011

13/069408

Hongqi LI - Boise ID, US
ANURAG JINDAL - Boise ID, US
Jin Lu - Boise ID, US

H01L 21/306
C11D 7/26

438692, 510175, 257E2123

A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents.

20120258596, Oct 11, 2012

Apr 6, 2011

13/080676

BRETT BUSCH - Boise ID, US
GOWRI DAMARLA - Boise ID, US
ANURAG JINDAL - Boise ID, US
CHIA-YEN HO - New Taipei City, TW
THY TRAN - Boise ID, US

H01L 21/306

438692, 257E2123

A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

20120314171, Dec 13, 2012

Jun 8, 2011

13/155810

Anurag Jindal - Boise ID, US
Kunal Parekh - Boise ID, US
Prashant Raghu - Boise ID, US
Nicolai Petrov - Boise ID, US
Mark Meldrim - Boise ID, US

G02F 1/1343
H01L 33/60
H01L 33/42

349139, 438 30, 438 29, 257E33072, 257E33064

In one or more embodiments, display devices having electrolessly plated conductors and methods are disclosed. One such embodiment is directed to a method of forming a reflective pixel array for a display device, including forming a plurality of conductive pads, each of the conductive pads corresponding to a reflective pixel, and electrolessly plating each of the conductive pads with a reflective conductor.

20120315754, Dec 13, 2012

Jun 8, 2011

13/155908

Xiaoyun Zhu - Boise ID, US
Dale W. Collins - Boise ID, US
Joseph Lindgren - Boise ID, US
Anurag Jindal - Boise ID, US

MICRON TECHNOLOGY, INC. - BOISE ID

H01L 21/768

438653, 257E21584

Interconnects containing ruthenium and methods of forming can include utilization of a sacrificial protective material. Planarization or other material removal operations can be performed on a substrate having a recess, the recess containing a ruthenium containing material along with the sacrificial protective material. The protective material is later removed, and a conductor can be filled in the remaining recess.

20130032870, Feb 7, 2013

Aug 3, 2011

13/197557

Anurag Jindal - Boise ID, US
Gowri Damarla - Boise ID, US
Roger W. Lindsay - Boise ID, US
Eric Blomiley - Boise ID, US

H01L 29/788
H01L 29/792
H01L 21/30
H01L 21/28
H01L 21/306

257315, 438593, 438696, 438584, 257324, 257E21209, 257E21219, 257E21211, 257E293, 257E29309

Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

20130320538, Dec 5, 2013

May 31, 2012

13/485539

Anurag Jindal - Boise ID, US
Hongqi Li - Boise ID, US

MICRON TECHNOLOGY, INC. - Boise ID

H01L 23/48
H01L 21/768

257751, 438667, 257774, 257E23011, 257E21586

A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides of the substrate. A first material is deposited to line and narrow the through-substrate via opening. The first material is etched to widen at least an elevationally outermost portion of the narrowed through-substrate via opening on the one side. After the etching, a conductive second material is deposited to fill the widened through-substrate via opening. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

20140004698, Jan 2, 2014

Jun 29, 2012

13/538272

Wayne H. Huang - Boise ID, US
Anurag Jindal - Boise ID, US

MICRON TECHNOLOGY, INC. - Boise ID

H01L 21/28

438653, 438672, 438667, 257E21158

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.

20140038414, Feb 6, 2014

Oct 9, 2013

14/049232

- Tao-Yuan Hsien, TW
GOWRI DAMARLA - Boise ID, US
ANURAG JINDAL - Boise ID, US
Chia-Yen Ho - New Taipei City, TW
THY TRAN - Boise ID, US

NANYA TECHNOLOGY CORP. - Tao-Yuan-Hsien

H01L 21/306

438692

A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.