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Anup P Jose

from San Jose, CA
Age ~44
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Also known as:
Anup Preethi Jose, Anup Preethis Jose, Jose Paul Anup, Jose P Anup
Phone and address:
772 Sirica Ct, San Jose, CA 95138
Related to:
Trisha Anup
Connected to:
Abraham Jose, 49Abreu R Jose, 52Achamma Jose, 65Adi R Jose, 47Aldo Jose, 47Amanda L Jose, 51Andino J Jose, 42Anie Jose, 65Anila P Jose, 50Anna M Jose, 57

Anup Jose Phones & Addresses

  • 772 Sirica Ct, San Jose, CA 95138
  • Acton, MA
  • New York, NY
  • Lowell, MA

Resumes

Resumes

Anup Jose Photo 1

Principal Engineer

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Location:
772 Sirica Ct, San Jose, CA 95138
Industry:
Semiconductors
Work:
Xilinx - San Jose, CA since Sep 2011
Staff Engineer, Serdes Technology Group
Kawasaki Microelectronics - San Jose, CA Sep 2010 - Sep 2011
Sr. Engineer
AMD - Boxborough, MA Jan 2006 - Aug 2010
Sr. Design Engineer
IBM Research - Autsin, TX Jun 2005 - Aug 2005
Summer intern
IBM Research - Yorktown Heights, NY Jun 2004 - Jul 2004
Summer intern
Education:
Columbia University - Fu Foundation School of Engineering and Applied Science 2001 - 2005
MS/PhD, Electrical Engineering Indian Institute of Technology, Madras 1997 - 2001
B.Tech, Electrical Engineering GREM School
Skills:
Analog
Pll
Serdes
Mixed Signal
Static Timing Analysis
Dll
Logic Design
Ocean Script
Perl
Matlab
Phase Locked Loop
Cmos
Leadership
Communication
Management
Teamwork
Languages:
English
Anup Jose Photo 2

Co-Founder And Chief Executive Officer

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Location:
San Jose, CA
Work:
Infusions Global
Co-Founder and Chief Executive Officer
Education:
University College of Teacher Education, Vocational Higher Secondary School Campus, Elanthoor, Pathanamthitta
Anup Jose Photo 3

Anup Jose

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Publications

Us Patents

Integrated Spectrum Analyzer Circuits And Methods For Providing On-Chip Diagnostics

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US Patent:
7446523, Nov 4, 2008
Filed:
Sep 21, 2006
Appl. No.:
11/524598
Inventors:
Keith Aelwyn Jenkins - Sleepy Hollow NY, US
Anup Paul Jose - New York NY, US
Scott Kevin Reynolds - Granite Springs NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 23/00
G01R 23/14
US Classification:
324 7619, 324 7623
Abstract:
Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which includes a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

Systems And Methods For On-Chip Signaling

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US Patent:
7548094, Jun 16, 2009
Filed:
Jan 17, 2007
Appl. No.:
11/654286
Inventors:
Kenneth L. Shepard - Ossining NY, US
Anup P. Jose - Acton MA, US
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H03K 19/0175
H03K 19/02
US Classification:
326 82, 326135
Abstract:
Systems and methods for on-chip signaling are disclosed. In some embodiments, an integrated circuit having on-chip signaling between a first component and a second component includes, a differential interconnect capable of coupling the first component to the second component, a driver capable of being coupled to the first component that sends data on the differential interconnect, a receiver capable of being coupled to the second component that receives the data, and a plurality of negative impedance converters capable of being coupled to the differential interconnect that provide loss compensation.

Integrated Spectrum Analyzer Circuits And Methods For Providing On-Chip Diagnostics

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US Patent:
7688058, Mar 30, 2010
Filed:
Sep 17, 2008
Appl. No.:
12/212247
Inventors:
Keith Aelwyn Jenkins - Sleepy Hollow NY, US
Anup Paul Jose - New York NY, US
Scott Kevin Reynolds - Granite Springs NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 23/00
G01R 23/14
US Classification:
324 7619, 324 7623
Abstract:
Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

Integrated Spectrum Analyzer Circuits And Methods For Providing On-Chip Diagnostics

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US Patent:
20060025946, Feb 2, 2006
Filed:
Jul 28, 2004
Appl. No.:
10/900733
Inventors:
Keith Jenkins - Sleepy Hollow NY, US
Anup Jose - New York NY, US
Scott Reynolds - Granite Springs NY, US
International Classification:
G01R 23/16
US Classification:
702076000
Abstract:
Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

Correlated Double Sampling Pixel Sensing Front End

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US Patent:
20210049951, Feb 18, 2021
Filed:
Oct 17, 2019
Appl. No.:
16/656423
Inventors:
- Yongin-si, KR
Anup P. Jose - San Jose CA, US
Gaurav Malhotra - Cupertino CA, US
Younghoon Song - Santa Clara CA, US
Mohamed Elzeftawi - San Jose CA, US
International Classification:
G09G 3/32
G01R 17/02
Abstract:
A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.

Estimation Of Pixel Compensation Coefficients By Adaptation

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US Patent:
20210049963, Feb 18, 2021
Filed:
Oct 18, 2019
Appl. No.:
16/657680
Inventors:
- Yongin-si, KR
Anup P. Jose - San Jose CA, US
Gaurav Malhotra - Cupertino CA, US
Younghoon Song - Santa Clara CA, US
Mohamed Elzeftawi - San Jose CA, US
International Classification:
G09G 3/3258
G09G 3/20
Abstract:
A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.

High-Efficiency Piecewise Linear Column Driver With Asynchronous Control For Displays

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US Patent:
20200202775, Jun 25, 2020
Filed:
Feb 22, 2019
Appl. No.:
16/283514
Inventors:
- Yongin-si, KR
Anup P. Jose - San Jose CA, US
International Classification:
G09G 3/3233
H03K 19/21
G09G 3/36
Abstract:
A device includes a segmented pull-up current source circuit including a first plurality of transistors, a segmented pull-down current source circuit including a second plurality of transistors, a comparator circuit configured to compare an output voltage level at the output of the device with a target voltage level and generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, the first plurality of AND gate circuits and a second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control an operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output.

Average And Decimate Operations For Bang-Bang Phase Detectors

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US Patent:
20190280591, Sep 12, 2019
Filed:
Aug 22, 2018
Appl. No.:
16/109645
Inventors:
- Yongin-si, KR
Amir Amirkhany - Sunnyvale CA, US
Anup P. Jose - San Jose CA, US
International Classification:
H02M 3/07
H03K 21/08
Abstract:
A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
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Anup P Jose from San Jose, CA, age ~44 Get Report