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Anthony J Casorso

from Westminster, CO
Age ~72
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Also known as:
Anthony J Casoro, Anthony Casarso
Phone and address:
4675 69Th Dr, Westminster, CO 80030
(303) 426-5674
Related to:
Kenneth Lee Fernandez, 64Lorna K Casorso, 73Mark A Casorso, 45Jeffery C Owens, 50Tanya Casorso, 47Tanya R Owens, 40Lorna G Casorso
Connected to:
Kavita B Casotti, 53Vincent G Casotti, 38Barry N Casowitz, 88Dan R Caspall, 80Brady Caspar, 62Chung Caspar, 43David O Caspar, 70Laura A Caspar, 54Olivier Caspar, 67Rita S Caspar, 82

Anthony Casorso Phones & Addresses

  • 4675 69Th Dr, Westminster, CO 80030 (303) 426-5674

Interests

reference requests, getting back in touch

Industries

Computer Hardware

Resumes

Resumes

Anthony Casorso Photo 1

Design Engineer At Western Digital

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Location:
Greater Denver Area
Industry:
Computer Hardware
Experience:
Western Digital (Public Company; 10,001 or more employees; WDC; Computer Hardware industry): Design Engineer,  (July 2008-Present) 

Publications

Us Patents

System And Method For A Distributed Shared Memory

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US Patent:
6862608, Mar 1, 2005
Filed:
Jul 17, 2001
Appl. No.:
09/906509
Inventors:
Craig A. Buhlman - Boulder CO, US
Anthony J. Casorso - Westminster CO, US
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
G06F015/167
US Classification:
709213, 709203, 711147
Abstract:
A system and method for a distributed shared memory. The system includes multiple processors, each processor transmitting write commands issued therefrom concerning a shared memory to each of the processors, such that each processor receives each shared memory write command transmitted. The system also includes multiple local memories, each local memory associated with one of the processors and having a copy of the shared memory, wherein each processor completes each received shared memory write command at its associated local memory such that the copies of the shared memory remain consistent at all times. The method includes transmitting write commands concerning the shared memory to each of the processors, such that each processor receives each shared memory write command transmitted, and completing each received shared memory write command at the associated local memory such that the copies of the shared memory remain consistent at all times.

Noise Tolerant Phase Locked Loop

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US Patent:
7489203, Feb 10, 2009
Filed:
Aug 24, 2006
Appl. No.:
11/510211
Inventors:
Anthony J. Casorso - Westminster CO, US
Assignee:
Quantum Corporation - San Jose CA
International Classification:
H03L 7/085
US Classification:
331 25, 327 5, 360 51, 375376
Abstract:
An apparatus and method for providing timing recovery under conditions of low signal to noise ratios (SNRs) is disclosed herein. A preliminary phase error signal is generated by comparing an input signal with a preliminary estimation of an output signal corresponding to the input signal. A correction signal is generated as a function of the output signal, input signal, and preliminary phase error signal. The preliminary phase error signal and the correction signal are combined to generate a final phase error signal.

Method And Apparatus For Ensuring Data Integrity In A Dynamically Mapped Data Storage Subsystem

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US Patent:
54043611, Apr 4, 1995
Filed:
Jul 27, 1992
Appl. No.:
7/919897
Inventors:
Anthony J. Casorso - Westminster CO
David P. Haldeman - Broomfield CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
H03M 1300
US Classification:
371 401
Abstract:
The dynamically mapped data storage subsystem generates a two error correction, three error detection code of extent sufficient to cover not only the data but also the corresponding memory address for each data record stored therein. The error correction code is transmitted and stored with the data within the data storage subsystem to ensure the integrity of both the data and its memory address.
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Anthony J Casorso from Westminster, CO, age ~72 Get Report