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Anoop J Mukker

from Folsom, CA
Age ~54
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Also known as:
Anoop S Mukker, Annop Mukker, Anoop Mukkar, Mukker Anoop
Phone and address:
1733 Langholm Way, Folsom, CA 95630
(916) 984-7691
Related to:
Pankaj K Garg, 58Nidhi P Sood, 48Nidhi Mukker, 50Nidhi Sood, 45Nidhi P Sood, 56
Connected to:
Lucille M Muklewicz, 97Tracy Muklewicz, 49Deep Muko, 50Pamela Mukoko, 38Christine C Mukolwe, 52Brian S Mukomela, 59Marjorie R Mukomela, 65Lydia Mukono, 43Jesca Mukora, 50Adefunke I Mukoro, 50

Anoop Mukker Phones & Addresses

  • 1733 Langholm Way, Folsom, CA 95630 (916) 984-7691 (916) 608-4405
  • 2400 Natoma Station Dr, Folsom, CA 95630 (916) 985-0327
  • 250 Mcadoo Dr, Folsom, CA 95630 (916) 608-4405
  • 3012 Raging River Dr, Austin, TX 78728
  • 12001 Metric Blvd, Austin, TX 78758
  • Sacramento, CA

Work

Company: Intel corporation Jul 1, 1997 Position: High speed io, low speed io, memory interfaces and storage technologies architect

Skills

Soc • Debugging • Asic • Rtl Design • Verilog • Embedded Systems • Vlsi • Systemverilog • Semiconductors • Ic • Static Timing Analysis • Mixed Signal • Cmos • Fpga • Eda • Storage Architecture • Usb • Pcie • Power Management • Mipi Mphy • Mipi Dphy

Industries

Semiconductors

Resumes

Resumes

Anoop Mukker Photo 1

High Speed Io, Low Speed Io, Memory Interfaces And Storage Technologies Architect

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Location:
1733 Langholm Way, Folsom, CA 95630
Industry:
Semiconductors
Work:
Intel Corporation
High Speed Io, Low Speed Io, Memory Interfaces and Storage Technologies Architect
Skills:
Soc
Debugging
Asic
Rtl Design
Verilog
Embedded Systems
Vlsi
Systemverilog
Semiconductors
Ic
Static Timing Analysis
Mixed Signal
Cmos
Fpga
Eda
Storage Architecture
Usb
Pcie
Power Management
Mipi Mphy
Mipi Dphy

Publications

Us Patents

Dynamically Activated Memory Controller Data Termination

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US Patent:
7009894, Mar 7, 2006
Filed:
Feb 19, 2004
Appl. No.:
10/784047
Inventors:
Anoop Mukker - Folsom CA, US
Zohar Bogin - Folsom CA, US
Dave Freker - Sacramento CA, US
Navneet Dour - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
365191, 36518505, 365 63
Abstract:
A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

Hardware Detected Command-Per-Clock

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US Patent:
7058752, Jun 6, 2006
Filed:
Dec 30, 2003
Appl. No.:
10/749183
Inventors:
Suryaprasad Kareenahalli - Folsom CA, US
Zohar B. Bogin - Folsom CA, US
Anoop Mukker - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711100, 711154, 345531, 345566
Abstract:
A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.

Deterministic Shut Down Of Memory Devices In Response To A System Warm Reset

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US Patent:
7181605, Feb 20, 2007
Filed:
Oct 24, 2003
Appl. No.:
10/693226
Inventors:
Zohar Bogin - Folsom CA, US
Surya Kareenahalli - Folsom CA, US
Anoop Mukker - Folsom CA, US
David Sastry - Folsom CA, US
Tuong Trieu - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/00
US Classification:
713 1, 710267, 711106, 714799
Abstract:
A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

Optimized Memory Addressing

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US Patent:
7230627, Jun 12, 2007
Filed:
Mar 8, 2004
Appl. No.:
10/796686
Inventors:
David E. Freker - Sacramento CA, US
Aditya Sreenivas - El Dorado Hills CA, US
Zohar Bogin - Folsom CA, US
Anoop Mukker - Folsom CA, US
Tuong Trieu - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G09G 5/399
G09G 5/39
G06F 13/00
US Classification:
345540, 345531, 345536, 345537
Abstract:
Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Optimized Memory Addressing

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US Patent:
7612780, Nov 3, 2009
Filed:
Apr 6, 2007
Appl. No.:
11/784342
Inventors:
David E Freker - Sacramento CA, US
Aditya Sreenivas - El Dorado Hills CA, US
Zohar Bogin - Folsom CA, US
Anoop Mukker - Folsom CA, US
Tuong Trieu - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G09G 5/399
G06F 13/00
G09G 5/39
US Classification:
345540, 345531, 345536, 345537
Abstract:
Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Method And Apparatus For Dedicating Cache Entries To Certain Streams For Performance Optimization

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US Patent:
7797492, Sep 14, 2010
Filed:
Feb 20, 2004
Appl. No.:
10/783621
Inventors:
Anoop Mukker - Folsom CA, US
Zohar Bogin - Folsom CA, US
Tuong Trieu - Folsom CA, US
Aditya Navale - El Dorado Hills CA, US
International Classification:
G06F 13/16
US Classification:
711129, 711124
Abstract:
A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.

Data Bridge And Bridging

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US Patent:
20020184428, Dec 5, 2002
Filed:
May 31, 2001
Appl. No.:
09/870808
Inventors:
Joseph Bennett - Roseville CA, US
Mikal Hunsaker - El Dorado Hills CA, US
Anoop Mukker - Folsom CA, US
Adit Tarmaster - Citrus Heights CA, US
International Classification:
G06F013/36
US Classification:
710/310000
Abstract:
The present invention is in the field of bridging transactions from one bus to a second bus. More particularly, embodiments of the present invention can enhance an interface between two buses by ordering split-completion transactions to one or more hosts.

Apparatus And A Method To Adjust Signal Timing On A Memory Interface

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US Patent:
20050190193, Sep 1, 2005
Filed:
Mar 1, 2004
Appl. No.:
10/791180
Inventors:
David Freker - Sacramento CA, US
Zohar Bogin - Folsom CA, US
Dour Navneet - Folsom CA, US
Anoop Mukker - Folsom CA, US
Tuong Trieu - Folsom CA, US
International Classification:
G06F013/00
G06F013/372
US Classification:
345534000
Abstract:
An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.
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Anoop J Mukker from Folsom, CA, age ~54 Get Report