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Ann M Woo

from Alcoa, TN
Age ~92
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Also known as:
Wayland Yin Woo, Ann M Terrazas, Wayland F Woo, Anna Woo
Related to:
Kenneth Holst, 95Wayland WooStephanie Callahan, 45Bonnie Fallos, 65
Connected to:
Ada J Woo, 91Aileen P Woo, 66Alden S Woo, 48Alyssa Woo, 40Ansley C Woo, 46Astra Woo, 45Audrey S Woo, 50Bella Woo, 36Beverly M Woo, 55Bo K Woo, 106

Ann Woo Phones & Addresses

  • Alcoa, TN
  • 8035 Oconnor Dr APT 4A, River Grove, IL 60171 (708) 452-0208
  • Cupertino, CA
  • 6212 Barry Ave, Chicago, IL 60634 (773) 622-7768 (708) 452-0208
  • 6212 W Barry Ave, Chicago, IL 60634 (773) 677-8964

Work

Company: Hill physicians medical group Address: 2401 Crow Canyon Rd Ste 130, San Ramon, CA 94583 Phones: (925) 820-8300 Position: Manager Industries: Management Services

Resumes

Resumes

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Ann Woo

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Ann Woo

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Manager At Att

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Position:
manager at ATT
Location:
United States
Industry:
Accounting
Work:
ATT
manager

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ann Woo
Manager
Hill Physicians Medical Group
Management Services
2401 Crow Canyon Rd Ste 130, San Ramon, CA 94583
Ann K. Woo
Executive, Principal
Chinese Performing Artists of America
Eating Place
6148 Bollinger Rd, San Jose, CA 95129
Ann Woo
Manager
Hill Physicians Medical Group
Management Services
2401 Crow Canyon Rd Ste 130, San Ramon, CA 94583

Publications

Us Patents

Cmos Power-On Reset Circuit Using Hysteresis

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US Patent:
55348041, Jul 9, 1996
Filed:
Feb 13, 1995
Appl. No.:
8/387688
Inventors:
Ann K. Woo - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 190948
US Classification:
327143
Abstract:
A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply includes a voltage clamping stage (14) and a hysteresis switching stage (16). The voltage clamping stage (14) is formed of an N-channel resistor (M1), a first resistor (R1), and a second resistor (R2). The hysteresis switching stage (16) includes a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1).

Incremental Output Current Generation Circuit

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US Patent:
56083149, Mar 4, 1997
Filed:
Apr 11, 1994
Appl. No.:
8/226163
Inventors:
Ann Woo - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G05F 116
US Classification:
323313
Abstract:
An incremental output current generation circuit is disclosed wherein a reference current and a reference voltage are established which follow a bias current which is then multiplied. A set of predetermined voltage reference points are established and the multiplied current supplied thereto. A ramping input voltage is compared to the established voltage referencing points by comparitors. The outputs of the comparators flag the highest voltage reference point which the value of the voltage exceeded. These outputs are sensed by a current generator thereby providing predetermined fractions of the reference current to be delivered at the output as the output source current. In such a manner, an incremental output source current is generated which is dependent on an input voltage level and predetermined incrementally by the value of an established reference current.

Input Voltage Protection System

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US Patent:
49300377, May 29, 1990
Filed:
Feb 16, 1989
Appl. No.:
7/311270
Inventors:
Ann K. Woo - Cupertino CA
Assignee:
Advaced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H02H 320
US Classification:
361 58
Abstract:
A static electricity protection system for use with a voltage sensitive MOS component having a gate input including a layer of oxide. A transmission gate having a source and a drain as an input and output, respectively, is connected to the MOS component gate input for protecting it from sudden electrical voltage surge discharges. The transmission gate source and drain include a layer of oxide substantially thicker than the oxide layer of the MOS component gate input.

Recovering Phase And Data From Distorted Duty Cycles Caused By Ecl-To-Cmos Translator

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US Patent:
52647455, Nov 23, 1993
Filed:
Aug 28, 1992
Appl. No.:
7/935886
Inventors:
Ann K. Woo - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 190175
H03K 19003
US Classification:
307475
Abstract:
A logic interface circuit for recovering phase and data information from ECL differential input signals of the NRZI type having distorted duty cycles caused by ECL-to-CMOS translators includes first and second ECL-to-CMOS translators (T1, T2), first and second delay circuits, and an output logic circuit The first delay circuit is formed of a first inverter (I1), a first delay network (D1), and a first NAND logic gate (N1). The second delay network includes a second inverter (I2), a second delay network (D2), and a second NAND logic gate (N2). The output logic circuit is formed of a third NAND logic gate. The interface circuit generates an output signal which is in the form of a pulse train whose cycle time can be detected for determining the frequency information and whose presence or absence of pulses can be detected for determining data information.

Cmos Digital-Controlled Delay Gate

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US Patent:
52276791, Jul 13, 1993
Filed:
Jan 2, 1992
Appl. No.:
7/815791
Inventors:
Ann K. Woo - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 1994
H03K 1920
US Classification:
307469
Abstract:
A CMOS digital-controlled delay gate is provided in which the propagation delay time can be precisely controlled by digital select control signals. The delay gate includes an inverter circuit section (12) formed of a plurality of CMOS inverters (12a-12n) each inverter having a P-channel transistor and an N-channel transistor and a control logic section (14, 16) which is responsive to the digital select control signals for changing the ratio of the total P-channel transistor size to the total N-channel transistor size in the enabled transistors. The input threshold voltage of the inverter circuit section is selectively changeable so as to produce a controllable propagation delay.

Power Supply Solution For Mixed Signal Circuits

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US Patent:
59173670, Jun 29, 1999
Filed:
Feb 11, 1997
Appl. No.:
8/798991
Inventors:
Ann K. Woo - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G05F 302
US Classification:
327537
Abstract:
There is provided an improved high-voltage generation circuit for use in a mixed signal circuit for multiplying an external power supply potential applied on its input to produce a higher output voltage at an output terminal. The high-voltage generation circuit is formed of a voltage multiplier circuit (114), a voltage comparator circuit (116), and switching circuitry (118). The voltage multiplier circuit is formed of a first stage (122) and at least one second stage (124) connected in series between the input terminal and the output terminal. The second stage is formed of a CMOS transistor (MP4) whose substrate is connected to a controlled node (N23). The voltage comparator circuit compares the external power supply potential and the output voltage and generates a control logic signal. The switching circuitry is responsive to the control logic signal for automatically connecting the controlled node to one of the external power supply potential and the output voltage so as to avoid forward-biasing of the substrate. As a result, there is achieved power savings and thus enhanced performance.

Programmable Driving Power Of A Cmos Gate

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US Patent:
52202160, Jun 15, 1993
Filed:
Jan 2, 1992
Appl. No.:
7/816683
Inventors:
Ann K. Woo - Cupertino CA
International Classification:
H03K 19094
H03K 1920
US Classification:
307469
Abstract:
A CMOS gate is provided which has a programmable driving power characteristic so that its propagation delay time can be varied by digital select control signals (S1-Sm). The CMOS gate includes a programmable inverter section (12) formed of a plurality of inverters (12a-12m), a switching logic control section (14), and a static inverter (16). The switching logic control signal section is responsive to the digital select control signals for selectively programming a certain number of the plurality of inverters to be enabled. In this manner, a certain number of the plurality of inverters will be wired in parallel with the static inverter in order to produce the desired amount of propagation delay time.

Static Pla Or Rom Circuit With Self-Generated Precharge

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US Patent:
47288272, Mar 1, 1988
Filed:
Dec 3, 1986
Appl. No.:
6/937572
Inventors:
Ann K. Woo - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 19017
US Classification:
307481
Abstract:
A static PLA circuit includes a logic gate portion, a precharge circuit portion and a feedback circuit portion. The feedback circuit portion is connected between the output of the logic gate portion and the input of the precharge circuit portion. The feedback circuit portion functions to delay the turn-on time of the precharge circuit portion when the output of the logic gate portion is making a high-to-low transition, thereby increasing the speed of the output transition.
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Ann M Woo from Alcoa, TN, age ~92 Get Report