Resumes
Resumes
Senior Design Engineer
View pageLocation:
Santa Clara, CA
Industry:
Semiconductors
Work:
Intel Corporation
Design Engineer
Intel Corporation Jun 2012 - Sep 2013
Design and Validation Engineer
Intel Corporation Jan 2012 - Jun 2012
Graduate Technical Intern
Innovium Inc. Jan 2012 - Jun 2012
Senior Design Engineer
Design Engineer
Intel Corporation Jun 2012 - Sep 2013
Design and Validation Engineer
Intel Corporation Jan 2012 - Jun 2012
Graduate Technical Intern
Innovium Inc. Jan 2012 - Jun 2012
Senior Design Engineer
Education:
Portland State University 2010 - 2012
Masters, Computer Engineering Department of Technology, Savitribai Phule Pune University 2005 - 2009
Bachelors, Engineering, Electronics
Masters, Computer Engineering Department of Technology, Savitribai Phule Pune University 2005 - 2009
Bachelors, Engineering, Electronics
Skills:
Systemverilog
Debugging
Testing
Asic
Verilog
Perl
Open Verification Methodology
C++
Application Specific Integrated Circuits
C
Vhdl
Rtl Design
Very Large Scale Integration
Debugging
Testing
Asic
Verilog
Perl
Open Verification Methodology
C++
Application Specific Integrated Circuits
C
Vhdl
Rtl Design
Very Large Scale Integration
Aniket Kakade
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