Andrew I Collins

8556165, Oct 15, 2013

May 5, 2006

11/381817

Jeffrey R. Kapis - Chandler AZ, US
Andrew W. Collins - Charlotte NC, US
Steffanie R. Gaus - Jacksonville FL, US
Naseem I. Khan - Stone Mountain GA, US

Bank of America Corporation - Charlotte NC

G06Q 40/00

235379, 705 38, 705 35

Method and System for Enabling Teller Presentation of Pre-Approved Credit Offers. Simultaneously with a teller transaction flow, pertinent customer information can be parsed and forwarded to a credit opportunity system such as may be operated by a credit bureau. If the customer qualifies, the appropriate details of the pre-approved credit offer can then returned to the teller system. The teller then has both a cue and the necessary information to sell a pre-approved product to the customer. Provisions can be made to dispose of the transaction in various ways, based on input by the teller as to the outcome of the offer to the customer. A server and other functionality disposed in a channel technology mid-tier can control the formatting and sending of offer inquiries.

20230090759, Mar 23, 2023

Sep 23, 2021

17/482747

- Santa Clara CA, US
Tarek A. IBRAHIM - Mesa AZ, US
Andrew COLLINS - Chandler AZ, US

H01L 23/64
H01L 23/14
H01L 23/48
H01L 21/50
H01F 3/02
H01F 3/10

Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

20230081139, Mar 16, 2023

Sep 15, 2021

17/475726

- Santa Clara CA, US
Chandra Mohan Jha - Tempe AZ, US
Andrew Paul Collins - Chandler AZ, US
Omkar G. Karhade - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 23/538
H01L 25/065
H01L 25/18
H01L 23/367
H01L 25/00

An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

20210225828, Jul 22, 2021

Apr 5, 2021

17/222923

- Santa Clara CA, US
Andrew COLLINS - Chandler AZ, US

H01L 25/18
H01L 23/538
H01L 23/00
G11C 29/04
H01L 23/48
H01L 23/367
H01L 21/48
H01L 25/00
H01L 25/065
H01L 23/13

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

20200105719, Apr 2, 2020

Sep 29, 2018

16/147742

- Santa Clara CA, US
Zhiguo QIAN - Chandler AZ, US
Prasad RAMANATHAN - Chandler AZ, US
Saikumar JAYARAMAN - Chandler AZ, US
Kemal AYGUN - Tempe AZ, US
Hector AMADOR - Chandler AZ, US
Andrew COLLINS - Chandler AZ, US
Jianyong XIE - Chandler AZ, US
Shigeki TOMISHIMA - Portland OR, US

H01L 25/065
H01L 25/10
H01L 25/00

Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

20200075567, Mar 5, 2020

Aug 31, 2018

16/119837

- Santa Clara CA, US
Andrew Collins - Chandler AZ, US

H01L 25/18
H01L 23/13
H01L 23/538
H01L 23/00
G11C 29/04
H01L 23/48
H01L 23/367
H01L 21/48
H01L 25/00
H01L 25/065

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.