Andre T Nasr

53465849, Sep 13, 1994

Jul 28, 1993

8/098164

Andre I. Nasr - Marlborough MA
Steven S. Cooperman - Southborough MA

Digital Equipment Corporation - Maynard MA

H01L 21306
H01L 21304

156636

Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.

49120611, Mar 27, 1990

Apr 4, 1988

7/176837

Andre I. Nasr - Marlboro MA

Digital Equipment Corporation - Maynard MA

H01L 21283
H01L 21318

437 44

A method of fabricating a SALICIDED self aligned metal oxide semiconductor device using a disposable silicon nitride spacer, metal silicide and a single implant step for the source, drain and gate regions is disclosed. The fabrication of the device is accomplished in seven major steps: First, on a substrate having an oxide layer, an undoped polysilicon layer defining the gate region is deposited. Second, an oxide layer is grown and then a silicon nitride layer is deposited. Third, the oxide and the silicon nitride layers are selectively etched, leaving the oxide and the nitride layers on the walls of the polysilicon gate region. Fourth, a cobalt layer is deposited on the wafer and processed to form cobalt silicide, after which the cobalt that did not come in contact with the silicon or the polysilicon gate region is removed. Fifth, the nitride layer on the walls of the gate region is removed. Sixth, a single ion implant step is used to form the N-channel Transistors of the device.

54948576, Feb 27, 1996

Jul 28, 1993

8/098533

Steven S. Cooperman - Southborough MA
Andre I. Nasr - Marlborough MA

Digital Equipment Corporation - Maynard MA

H01L 21304
H01L 2176

437228

A new method for planarization of shallow trenches is presented. Shallow trenches are patterned into a semiconductor substrate that has been coated with a layer of silicon nitride. A conformal coating of oxide is deposited onto the wafer to fill the trenches. A thin layer of etch-stop silicon and a second layer of oxide are then deposited. The second layer of oxide is patterned with a filler mask using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.

52661563, Nov 30, 1993

Jun 25, 1992

7/904389

Andre I. Nasr - Marlboro MA

Digital Equipment Corporation - Maynard MA

H01L 21312

156656

Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi. sub. 2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi. sub. 2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.

55630960, Oct 8, 1996

Nov 20, 1995

8/560853

Andre I. Nasr - Marlboro MA

Digital Equipment Corporation - Maynard MA

H01L 2144

437186

In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided.