Anand J Reddy

7727885, Jun 1, 2010

Aug 29, 2006

11/511698

Phillip Daniel Matz - Murphy TX, US
Sopa Chevacharoenkul - Richardson TX, US
Basab Chatterjee - Allen TX, US
Anand Reddy - Dallas TX, US
Kenneth Joseph Newton - McKinney TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/44

438634, 438653, 438799, 438678, 257E21586, 257E21579, 257E21584

A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

7732324, Jun 8, 2010

Dec 20, 2007

11/961464

Sameer K. Ajmera - Richardson TX, US
Changming Jin - Plano TX, US
Anand J. Reddy - Palo Alto CA, US
Tae S. Kim - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/469

438624, 438763, 438786, 438791, 438792, 257E21493

One aspect of the invention provides a method of forming a semiconductor device (). One aspect includes forming transistors () on a semiconductor substrate (), forming a first interlevel dielectric layer () over the transistors (), and forming metal interconnects () within the first interlevel dielectric layer (). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer () over the metal interconnects () and the first interlevel dielectric layer () within a deposition tool. An adhesion layer () is formed on the SiCN layer (), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer () is formed over the adhesion layer ().

20040229388, Nov 18, 2004

May 15, 2003

10/438651

Richard Guldi - Dallas TX, US
Howard Tigelaar - Allen TX, US
Anand Reddy - Dallas TX, US

H01L021/00
H01L021/66

438/014000, 438/018000

A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

20060033503, Feb 16, 2006

Aug 9, 2005

11/199664

Richard Guldi - Dallas TX, US
Howard Tigelaar - Allen TX, US
Anand Reddy - Dallas TX, US

H01L 21/00
G01R 31/00

324500000, 438005000

A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

20170179326, Jun 22, 2017

Dec 21, 2015

14/976900

- San Mateo CA, US
Anand J. Reddy - Castro Valley CA, US
Chunguang Xiao - Fremont CA, US
Jiunn Benjamin Heng - Los Altos Hills CA, US

SolarCity Corporation - San Mateo CA

H01L 31/0725
H01L 31/18

One embodiment of the invention can provide a system for fabricating a photovoltaic structure. During fabrication, the system can form a sacrificial layer on a first side of a Si substrate; load the Si substrate into a chemical vapor deposition tool, with the sacrificial layer in contact with a wafer carrier; and form a first doped Si layer on a second side of the Si substrate. The system subsequently can remove the sacrificial layer; load the Si substrate into a chemical vapor deposition tool, with the first doped Si layer facing a wafer carrier; and form a second doped Si layer on the first side of the Si substrate.

20160163888, Jun 9, 2016

Sep 17, 2015

14/857653

- San Mateo CA, US
Anand J. Reddy - Castro Valley CA, US

SolarCity Corporation - San Mateo CA

H01L 31/0224
H01L 31/05

One embodiment of the present invention provides an electrode grid positioned at least on a first surface of a photovoltaic structure. The electrode grid can include a number of finger lines and an edge busbar positioned at an edge of the photovoltaic structure. The edge busbar can include one or more paste-alignment structures configured to facilitate confinement of conductive paste used for bonding the edge busbar to an opposite edge busbar of an adjacent photovoltaic structure.

20150090314, Apr 2, 2015

Dec 8, 2014

14/563867

- Fremont CA, US
Peter P. Nguyen - San Jose CA, US
Jiunn Benjamin Heng - San Jose CA, US
Anand J. Reddy - Castro Valley CA, US
Zheng Xu - Pleasanton CA, US

H01L 31/05
H01L 31/18
H01L 31/0224

136244, 136256, 438 66

One embodiment of the present invention provides a solar panel. The solar panel includes a plurality of subsets of solar cells. The solar cells in a subset are coupled in series, and the subsets of solar cells are coupled in parallel. The number of solar cells in a respective subset is sufficiently large such that the output voltage of the solar panel is substantially the same as an output voltage of a conventional solar panel with all of its substantially square shaped solar cells coupled in series.