Search

Amitabh Menon

from Lewisville, TX
Get Report
Also known as:
A Menon
Connected to:
Abilash Menon, 41Ajay Menon, 34Akash Menon, 31Akhila A Menon, 34Anitha Menon, 61Anna S Menon, 34Anup A Menon, 45Appen P Menon, 74Archana Menon, 39Dhanya C Menon, 45

Amitabh Menon Phones & Addresses

  • Lewisville, TX
  • 12250 Kirkwood Rd, Stafford, TX 77477 (281) 313-2542
  • Houston, TX
  • Dallas, TX
  • Milpitas, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Amitabh Menon
Principal
Menon Amitabh
Business Services at Non-Commercial Site
505 Benwick Way, Frisco, TX 75056

Publications

Us Patents

Register File Bypass With Optional Results Storage And Separate Predication Register File In A Vliw Processor

View page
US Patent:
7725687, May 25, 2010
Filed:
Jun 27, 2007
Appl. No.:
11/769191
Inventors:
Amitabh Menon - Lewisville TX, US
David J. Hoyle - Sugarland TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 9/34
US Classification:
712218
Abstract:
This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.

Multiple Patches To On-Chip Rom In A Processor With A Multilevel Memory System Without Affecting Performance

View page
US Patent:
7269707, Sep 11, 2007
Filed:
Jan 9, 2004
Appl. No.:
10/754252
Inventors:
Amitabh Menon - Stafford TX, US
Subash Chandar Govindarajan - Tamil Nadu, IN
Venkatesh Natarajan - Karnataka, IN
Vijay Sindagi - Karnataka, IN
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 12/08
US Classification:
711202, 711102, 711118, 711122, 717168
Abstract:
A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the ROM to the RAM. The ROM address space is mapped to RAM via a set of configuration registers. This permits patched ROM program code and data table to be stored in on-chip RAM. The patched code and configuration data is stored in an off-chip non-volatile memory. This patch code and the configuration to use is loaded into the RAM and configuration registers on system bootstrap procedure.

Vector Predicates For Sub-Word Parallel Operations

View page
US Patent:
20080016320, Jan 17, 2008
Filed:
Jun 27, 2007
Appl. No.:
11/769198
Inventors:
Amitabh Menon - Lewisville TX, US
David Hoyle - Sugarland TX, US
International Classification:
G06F 15/00
US Classification:
712022000, 712E09001
Abstract:
This invention uses vector predicate registers to control conditional execution of instructions for vector elements within a data word. A particular vector predicate registers is addressed via a register index. The state of bits of the vector predicate register controls whether a corresponding sub-word operation is executed or inhibited.

Inter-Cluster Communication Network And Heirarchical Register Files For Clustered Vliw Processors

View page
US Patent:
20090006816, Jan 1, 2009
Filed:
Jun 27, 2007
Appl. No.:
11/769212
Inventors:
David J. Hoyle - Sugarland TX, US
Amitabh Menon - Lewisville TX, US
International Classification:
G06F 9/30
US Classification:
712215, 712E09028
Abstract:
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.

Multilayer Arbitration For Access To Multiple Destinations

View page
US Patent:
20120072631, Mar 22, 2012
Filed:
Aug 18, 2011
Appl. No.:
13/212384
Inventors:
Kai Chirca - Richardson TX, US
Timothy D. Anderson - Dallas TX, US
Amitabh Menon - Milpitas CA, US
International Classification:
G06F 13/366
US Classification:
710244
Abstract:
An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.

Prefetcher With Arbitrary Downstream Prefetch Cancelation

View page
US Patent:
20120072702, Mar 22, 2012
Filed:
Sep 15, 2011
Appl. No.:
13/233028
Inventors:
Matthew D. Pierson - Murphy TX, US
Joseph R.M. Zbiciak - Arlington TX, US
Kai Chirca - Richardson TX, US
Amitabh Menon - Lewisville TX, US
Timothy D. Anderson - Dallas TX, US
International Classification:
G06F 9/312
US Classification:
712207, 712E09033
Abstract:
A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.

Memory Controller With Automatic Error Detection And Correction

View page
US Patent:
20120072796, Mar 22, 2012
Filed:
Sep 20, 2011
Appl. No.:
13/237917
Inventors:
Kai Chirca - Richardson TX, US
Timothy D. Anderson - Dallas TX, US
Amitabh Menon - Lewisville TX, US
International Classification:
G11C 29/04
G06F 11/16
US Classification:
714723, 714E11056
Abstract:
A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.

Flexible Memory Protection And Translation Unit

View page
US Patent:
20120191899, Jul 26, 2012
Filed:
Sep 21, 2011
Appl. No.:
13/239063
Inventors:
Joseph R. M. Zbiciak - Arlington TX, US
Amitabh Menon - Lewisville TX, US
Timothy D. Anderson - Dallas TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
G06F 12/14
US Classification:
711103, 711E12093, 711E12008
Abstract:
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.
Control profile
Amitabh Menon from Lewisville, TX Get Report