Amit N Shah

6895525, May 17, 2005

Aug 20, 1999

09/378425

Bruce James Wilkie - Georgetown TX, US
Amit Sumanlal Shah - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F001/04
G06F011/00

713503, 713500, 714 48, 714700

An electronic system includes a reference clock that generates a reference clock signal, at least one, phase-locked loop clock generator that synthesizes a derivative clock signal from the reference clock signal, and at least one digital circuit timed by the derivative clock signal. In addition, the electronic system includes a phase-locked loop clock synthesis fault detector having a phase detector and data storage for storing a historical indication of the phase of the derivative clock signal synthesized from the reference clock signal. The phase detector detects a change of phase of the derivative clock signals relative to the historical indication of the phase and, in response to this detection, signals that a clock synthesis fault has occurred.

7574482, Aug 11, 2009

Oct 31, 2003

10/699092

David Allen Brown - Austin TX, US
Amit M. Shah - Austin TX, US

Agere Systems Inc. - Allentown PA

G06F 15/16
G06F 12/02
G06F 13/00

709217, 709218, 711 1, 711152

An internal memory controller of a network processor or other type of processor controls access of processor clients to memory instances of an internal memory of the processor. The internal memory controller includes a configurable switching element that is connectable between the clients and the memory instances, and is operative to control access of particular ones of the clients to particular ones of the memory instances. Generally, the configurable switching element is configurable to connect any one of at least a subset of the clients to each of at least a subset of the memory instances. In a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of one or more memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of one or more memory instances, with the second set being different than the first set.

7729388, Jun 1, 2010

Mar 12, 2004

10/799239

David Allen Brown - Austin TX, US
Amit Mahendra Shah - Austin TX, US

Agere Systems Inc. - Allentown PA

H04J 3/26

370535, 370359, 370389, 3703953

A processor includes at least a portion of a first split transmit and receive media access controller (MAC), the split transmit and receive MAC having a transmit unit and a receive unit physically separated from one another. An interface for directing signals between the transmit unit and the receive unit of the first split transmit and receive MAC is configurable to multiplex the signals with other signals directed between a transmit unit and a receive unit of at least a second split transmit and receive MAC. The interface may comprise a plurality of channels, each having one or more ports associated therewith, wherein a given signal to be directed between transmit and receive units of a given split transmit and receive MAC is assigned to a particular channel and port of the interface.

58058362, Sep 8, 1998

Dec 10, 1996

8/762901

Steven Russell Barnhart - Austin TX
Amit Sumanlal Shah - Round Rock TX
Kenneth Lundy Ward - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1336

395287

An apparatus for equalizing grants of a primary bus to a plurality of primary devices and secondary devices is provided. The apparatus comprises a primary bus bridge to arbitrate grants of the primary bus among a plurality of primary devices attached to the primary bus and a secondary bus bridge to arbitrate grants of the primary bus among a plurality of secondary devices attached to a secondary bus. A logic device is also provided to equalize grants of the primary bus to the primary and the secondary devices.

58386815, Nov 17, 1998

Jan 24, 1996

8/590970

Flavio Bonomi - Palo Alto CA
Kent H. Headrick - Newark CA
Amit Shah - Sunnyvale CA

H04L 1256

370395

A system and method for routing data between input and output ports in an ATM node of a packet-switched network allocates port capacity in accordance with the requirements of the users connected to the ports. Capacity may be allocated either dynamically in real time, according to a fixed predetermined schedule, or according to certain characteristics of the data awaiting transfer between users, such as the length or type of data. The system and method optimize the utilization of system resources by enabling ports having a physical capacity which substantially exceeds the capacity of a conventional ATM switch to be interconnected for data transfer.

20210133019, May 6, 2021

Nov 1, 2019

16/671851

- Round Rock TX, US
Amit Shah - Austin TX, US
Yuwei Cai - Austin TX, US

G06F 11/07
G06F 9/52

An information handling system includes a memory controller with an error logger, and a DIMM coupled to the memory controller via a memory channel. The DIMM includes a non-volatile memory device mapped to include event blocks that store error information associated with memory events occurring the memory controller, the DIMM, and the memory channel. Each event block includes a flag field and a data field. The error logger receives an indication that a memory event has occurred, reads first flag information from a flag field of an event block, determines whether the event block is locked based upon the first flag information, and if the event block is not locked, then writes second flag information to the flag field and writes event information to a data field of the event block. The event information describes the memory event.

20200043529, Feb 6, 2020

Aug 3, 2018

16/054971

- Round Rock TX, US
Vadhiraj Sankaranarayanan - Austin TX, US
Amit Sumanlal Shah - Austin TX, US
Mark Andrew Dykstra - Round Rock TX, US

G11C 5/04
G06F 1/20
G11C 11/4078
G06F 11/07
G06F 11/30

A dual in-line memory module (DIMM) thermal control system for intelligent DIMM thermal controls for maximum uptime may include a memory subsystem. The memory subsystem may include a first DIMM and a first serial presence detect (SPD) module associated with the first DIMM. The DIMM thermal control system may also include a baseboard management controller (BMC). The BMC may, when a first DIMM failure of the first DIMM may be detected, record a first failure event in a first failure events log of the first SPD module. The first failure event may comprise the first DIMM failure and associated first thermal telemetry data of the first DIMM. The BMC may also adjust DIMM thermal control settings to reduce temperature of the first DIMM based on the first failure events log including at least the first failure event.

20190266036, Aug 29, 2019

Feb 23, 2018

15/903844

- Round Rock TX, US
Amit S. Shah - Austin TX, US
Huong T. Nguyen - Cedar Park TX, US
Vijay B. Nijhawan - Austin TX, US
Vadhiraj Sankaranarayanan - Austin TX, US
Mark L. Farley - Austin TX, US
Andrew Butcher - Cedar Park TX, US

G06F 11/07
G06F 3/06

An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.