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Amit Y Narayan

from Cupertino, CA
Age ~53
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Also known as:
Amit Naryan
Phone and address:
21574 Castleton St, Cupertino, CA 95014
Related to:
Bryan D Jensen, 37Angela Lynn Jenson, 62Catherine Winters, 70David D Jensen, 74Catherine Salas, 70Vikerant Nayaran
Connected to:
Akila Narayanan, 39Amudha Narayanan, 55Anthony J Narayan, 47Aparna Narayan, 41Arun K Narayan, 58Bhagya K Narayan, 51Bharath Narayan, 36Bichitra Narayan, 81Chakravarthi V Narayanan, 66David D Narayan, 73

Amit Narayan Phones & Addresses

  • 21574 Castleton St, Cupertino, CA 95014
  • San Carlos, CA
  • 2603 Hastings Shore Ln, Redwood City, CA 94065
  • 3420 Santa Clara St, El Cerrito, CA 94530
  • 1063 Morse Ave, Sunnyvale, CA 94089
  • San Mateo, CA
  • Berkeley, CA
  • Santa Clara, CA

Resumes

Resumes

Amit Narayan Photo 1

Technologist, Innovator, Entrepreneur

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Position:
Founder / CEO at AutoGrid Systems - "Turning Big Data Into Power"
Location:
San Francisco Bay Area
Industry:
Renewables & Environment
Work:
AutoGrid Systems - "Turning Big Data Into Power" since Jun 2010
Founder / CEO
Stanford University Jul 2010 - Jul 2012
Director, Smart Grid Research in Modeling & Simulation
Magma Design Automation Sep 2006 - Jun 2010
Vice President, Product Development
Berkeley Design Automation Jul 2003 - Sep 2006
Founder and Vice President of Engineering
Berkeley Design Automation Oct 2001 - Jul 2003
Founder and CEO
Education:
University of California, Berkeley 1993 - 1998
Ph.D., Electrical Engineering and Computer Sciences Indian Institute of Technology, Kanpur 1989 - 1993
B.Tech., Electrical Engineering
Skills:
Product Management
Smart Grid
Entrepreneurship
Semiconductors
Renewable Energy
Start-ups
Business Development
Executive Management
Clean Technology
Amit Narayan Photo 2

Founder And Chief Executive Officer

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Location:
242 Exeter Ave, San Carlos, CA 94070
Industry:
Renewables & Environment
Work:
Stanford University Jul 2010 - Jul 2012
Director, Smart Grid Research In Modeling and Simulation
Autogrid Systems Enabling A Smarter Energy Internet"​ Jul 2010 - Jul 2012
Founder and Chief Executive Officer - Autogrid Systems
Autogrid Systems Turning Big Data Into Power Jul 2010 - Jul 2012
Founder and Chief Executive Officer
Magma Design Automation Sep 2006 - Jun 2010
Vice President, Product Development
Berkeley Design Automation Jul 2003 - Sep 2006
Founder and Vice President of Engineering
Education:
University of California, Berkeley 1993 - 1998
Doctorates, Doctor of Philosophy, Electrical Engineering Indian Institute of Technology, Kanpur 1989 - 1993
Bachelors, Bachelor of Technology, Electrical Engineering University of California
Doctorates, Doctor of Philosophy
Skills:
Start Ups
Product Management
Entrepreneurship
Semiconductors
Business Development
Strategy
Management
Renewable Energy
Smart Grid
Mobile Devices
Product Development
Strategic Partnerships
Software Development
Mergers and Acquisitions
Analytics
Simulations
Venture Capital
Product Marketing
Integration
Leadership
Program Management
Executive Management
Eda
Energy
Competitive Analysis
Crm
Clean Technology
Business Strategy
New Business Development
Ic
Saas
Asic
Business Planning
Cleantech
Integrated Circuit Design
Automation
Go To Market Strategy
Integrated Circuits
Languages:
English
Amit Narayan Photo 3

Amit Narayan

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Location:
San Francisco Bay Area
Industry:
Internet

Business Records

Name / Title
Company / Classification
Phones & Addresses
Amit Narayan
Managing
Narayan Ventures, LLC
Consulting
7083 Hollywood Blvd, Los Angeles, CA 90028
21574 Castleton St, Cupertino, CA 95014
Amit Narayan
Chief Executive Officer
Autogrid
Business Services · Business Services Electrical Contractor
255 Shoreline Dr, Redwood City, CA 94065
960 San Antonio Rd, Palo Alto, CA 94303
Amit Narayan
Chief Executive Officer, President
AutoGrid Systems
Computer Software · Prepackaged Software Services
255 Shoreline Dr SUITE 350, Redwood City, CA 94065
21574 Castleton St, Cupertino, CA 95014
2765 Sand Hl Rd, Menlo Park, CA 94025
(650) 802-8840
Amit Narayan
Director
Berkeley Design Automation
Semiconductors · Computer Integrated Systems Design · Integrated Circuits · Other Technical Consulting Svcs · Computer Systems Design Services
2500 Augustine Dr SUITE #201, Santa Clara, CA 95054
2902 Stender Way, Santa Clara, CA 95054
(408) 496-6600
Amit Narayan
Managing
Ikarus Media LLC
Internet Media Company · Communication Services
1578 Blossom Hl Rd, San Jose, CA 95118

Publications

Us Patents

Circuit Verification

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US Patent:
7028279, Apr 11, 2006
Filed:
May 23, 2003
Appl. No.:
10/444782
Inventors:
Jawahar Jain - Santa Clara CA, US
Subramanian K. Iyer - Austin TX, US
Amit Narayan - Redwood City CA, US
Debashis Sahoo - Stanford CA, US
Christian Stangier - Los Altos CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 9/45
G06F 17/50
US Classification:
716 5, 716 2, 716 3, 716 4, 716 7
Abstract:
In one embodiment, a system for verifying a circuit using a scheduling technique includes one or more partitioned ordered binary decision diagram (POBDD) modules that collectively generate one or more POBDDs. Each POBDD corresponds to one or more partitions of a state space of the circuit and includes a number of states and a number of nodes in the partition. The system also includes one or more cost metrics modules that collectively determine a processing cost of each of the partitions of each of the POBDDs. The system also includes one or more scheduling modules that collectively schedule processing of the partitions of the POBDDs for semiformal verification of a circuit. The schedule is based, at least in part, on the determined processing costs of the partitions of the POBDDs.

System And Method For Executing Image Computation Associated With A Target Circuit

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US Patent:
7032197, Apr 18, 2006
Filed:
Jun 4, 2003
Appl. No.:
10/454207
Inventors:
Jawahar Jain - Santa Clara CA, US
Subramanian K. Iyer - Austin TX, US
Amit Narayan - Redwood City CA, US
Debashis Sahoo - Stanford CA, US
Christian Stangier - Los Altos CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 17/50
US Classification:
716 5, 716 4, 716 7
Abstract:
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more operations may be executed in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit. An image associated with the target circuit may be partitioned into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure. An analysis may be computed of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.

Determining One Or More Reachable States In A Circuit Using Distributed Computing And One Or More Partitioned Data Structures

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US Patent:
7216312, May 8, 2007
Filed:
Nov 7, 2003
Appl. No.:
10/704234
Inventors:
Jawahar Jain - Santa Clara CA, US
Amit Narayan - Redwood City CA, US
Yoshihisa Kojima - Kawasaki, JP
Takaya Ogawa - Urayasu, JP
Subramanian K. Iyer - Austin TX, US
Debashis Sahoo - Stanford CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
In one embodiment, a method for determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures includes, at a first one of multiple computing systems, receiving a first partition of a circuit. The first partition corresponds to a first binary decision diagram (BDD) having a first density. The method includes performing a first reachability analysis on the first partition using the first BDD until a fixed point in the first partition has been reached and, if, during the first reachability analysis, the size of the first BDD exceeds a threshold, discarding the first BDD. The method includes communicating with at least one second one of the multiple computing systems. The second one of the multiple computing systems has received a second partition of the circuit. The second one of the multiple computing systems has performed a second reachability analysis on the second BDD without discarding the second BDD.

Method And Apparatus For Steady State Analysis Of A Voltage Controlled Oscillator

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US Patent:
7332974, Feb 19, 2008
Filed:
Jan 27, 2005
Appl. No.:
11/045241
Inventors:
Amit Mehrotra - Mountain View CA, US
Amit Narayan - San Carlos CA, US
Assignee:
Berkeley Design Automation, Inc. - Santa Clara CA
International Classification:
G06F 17/50
G01R 23/06
US Classification:
331 44, 703 14, 708804
Abstract:
A computer-implemented method computes the steady-state and control voltage of a voltage controlled oscillator, given a known frequency or a known period of oscillation of the voltage controlled oscillator. Differential algebraic equations representative of the voltage controlled oscillator are generated, where the differential algebraic equations includes a known period or frequency of oscillation and an unknown control voltage of the voltage controlled oscillator. The differential algebraic equations are modified using a finite difference method, a shooting method, or a harmonic balance method, to obtain a set of matrix equations corresponding to the differential algebraic equations. A solution to the matrix equations is obtained using a Krylov subspace method, using a preconditioner for the Krylov subspace method that is derived from a Jacobian matrix corresponding to the matrix equations, where the solution includes the control voltage of the voltage controlled oscillator in steady state.

Circuit Verification

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US Patent:
7571403, Aug 4, 2009
Filed:
Apr 10, 2006
Appl. No.:
11/279177
Inventors:
Jawahar Jain - Santa Clara CA, US
Subramanian K. Iyer - Austin TX, US
Amit Narayan - Redwood City CA, US
Debashis Sahoo - Stanford CA, US
Christian Stangier - Los Altos CA, US
Assignee:
Fujitsu Limited - Kanagawa
International Classification:
G06F 17/50
US Classification:
716 5, 716 7
Abstract:
In one embodiment, a method for verifying one or more particular properties of a circuit using a learning strategy to determine suitable values of particular verification parameters includes classifying each of multiple properties of a circuit according to circuit size and selecting a candidate property from the properties. The candidate property set includes one or more particular properties from each property class. The method also includes attempting to verify one or more particular properties of the circuit using the candidate property set and particular values of particular verification parameters. The method also includes determining suitable values of the particular verification parameters according the attempted verification of the particular properties of the circuit using the candidate property set and the particular values of the particular verification parameters.

System And Method For Evaluating An Erroneous State Associated With A Target Circuit

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US Patent:
7788556, Aug 31, 2010
Filed:
Mar 17, 2003
Appl. No.:
10/390982
Inventors:
Jawahar Jain - Santa Clara CA, US
Subramanian K. Iyer - Austin TX, US
Amit Narayan - Redwood City CA, US
Debashis Sahoo - Stanford CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G01R 31/28
US Classification:
714724, 703 14, 716 4
Abstract:
A method for evaluating an erroneous state associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are executed using the information in order to identify an erroneous state associated with a sub-space within the target circuit. A path associated with the erroneous state is identified. The path reflects a correlation between an initial state associated with the erroneous state and a point where the erroneous state was encountered.

System And Method For Verifying A Plurality Of States Associated With A Target Circuit

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US Patent:
20040093570, May 13, 2004
Filed:
Mar 17, 2003
Appl. No.:
10/391282
Inventors:
Jawahar Jain - Santa Clara CA, US
Amit Narayan - Redwood City CA, US
Subramanian Iyer - Austin TX, US
Debashis Sahoo - Stanford CA, US
Assignee:
Fujitsu Limited
International Classification:
G06F017/50
US Classification:
716/005000
Abstract:
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are then executed using the information in order to generate a first set of states at a first depth associated with a sub-space within the target circuit. Bounded model checking may be executed using the first set of states in order to generate a second set of states at a second depth associated with the sub-space within the target circuit. The first set of states may be used as a basis for the second set of states such that the second depth is greater than the first depth.

Determining Load Reductions In Demand Response Systems

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US Patent:
20150192945, Jul 9, 2015
Filed:
Sep 14, 2012
Appl. No.:
14/345391
Inventors:
Amit Narayan - Cupertino CA, US
Abishek Bahl - San Francisco CA, US
Vijay Srikrishna Bhat - San Francisco CA, US
Assignee:
AUTOGRID INC. - Redwood Shores CA
International Classification:
G05F 1/66
G05B 15/02
Abstract:
The present invention relates to a signal processing technique for characterization of baseline noise, and for determining load reduction in presence of baseline noise. The method utilizes sparse signal processing algorithm to recover demand resource response signal and a plurality of SNR enhancement strategies are then applied to demand resource response signal for enhancing the signal to noise ratio.
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Amit Y Narayan from Cupertino, CA, age ~53 Get Report