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Ameya S Limaye

from Portland, OR
Age ~44
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Also known as:
Ameya L Limaye, Ameya Limayo, Limaye Ameya
Phone and address:
4522 NW 133Rd Ave, Portland, OR 97229
Related to:
Sasha LimayeSahil Limaye
Connected to:
Arati U Limaye, 47Himani R Limaye, 47Janardan S Limaye, 89Rajeev S Limaye, 61Rajendra V Limaye, 58Rajiv V Limaye, 66Smita S Limaye, 47Vasant Limaye, 62Vikram R Limaye, 78Edwin Limaylla, 52

Ameya Limaye Phones & Addresses

  • 4522 NW 133Rd Ave, Portland, OR 97229
  • Chandler, AZ
  • 1166 Atlantic Ctr, Atlanta, GA 30318
  • Marietta, GA
  • Maricopa, AZ
  • Jamestown, NY
  • 1166 Atlantic Dr NW, Atlanta, GA 30318

Resumes

Resumes

Ameya Limaye Photo 1

System Architect

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Intel Corporation
System Architect
Ciba Vision May 2003 - Aug 2003
Summer Intern
Education:
Georgia Institute of Technology 2004 - 2007
Doctorates, Doctor of Philosophy, Mechanical Engineering Georgia Institute of Technology 2002 - 2004
Master of Science, Masters, Mechanical Engineering College of Engineering Pune 1998 - 2002
Bachelor of Engineering, Bachelors, Mechanical Engineering
Skills:
Finite Element Analysis
Simulations
Design of Experiments
Ansys
Matlab
Simulink
Mechanical Engineering
Heat Transfer
Abaqus
Labview
Research and Development
Continuum Mechanics
Mechanics of Materials
Rapid Prototyping
Python
Pro Engineer
Solidworks
Afm
Scanning Electron Microscopy
Ameya Limaye Photo 2

Ameya Limaye

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Publications

Us Patents

Method For Making Ophthalmic Devices Using Single Mold Stereolithography

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US Patent:
20090250828, Oct 8, 2009
Filed:
Mar 24, 2009
Appl. No.:
12/409700
Inventors:
David William Rosen - Marietta GA, US
Scott Johnston - St. Louis MO, US
Ameya S. Limaye - Chandler AZ, US
Robert E. Schwerzel - Alpharetta GA, US
Allen Gilliard - Buford GA, US
International Classification:
B29D 11/00
B29C 67/00
US Classification:
264 138, 425162
Abstract:
A method for manufacturing an ophthalmic lens comprising introducing a volume of photocurable lens material into a container, wherein said container comprises a mold surface. The method further comprises creating a digital 3-D mathematical model defining corrective needs of an eye and projecting programmed patterns of UV light through said mold via a pattern generator, wherein said programmed patterns of UV light cure said photocurable lens material into a lens shape defined by said mold surface and said digital model.

Integrated Circuit Thermal Throttling With Workload Adapted Thermal Sensor Maximum Temperature

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US Patent:
20200401199, Dec 24, 2020
Filed:
Jul 10, 2020
Appl. No.:
16/926402
Inventors:
- Santa Clara CA, US
Ameya Limaye - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/20
G06F 1/324
Abstract:
A method and apparatus for integrated circuit (IC) thermal throttling is described. In one embodiment, the apparatus comprises a plurality of thermal sensors, each of the plurality of thermal sensors being located in an area in the IC to record a die temperature at a location in its associated area; and a thermal controller coupled to the plurality of thermal sensors to perform thermal throttling of the IC to reduce the temperature of the IC in response to the die temperature recorded by any one temperature sensors of the plurality of thermal sensors being greater than an individual temperature threshold for said any one temperature sensor, the individual temperature threshold for each temperature sensor being based on a maximum temperature allowed for the area in the IC in which said each thermal sensor is located and power supplied to a plurality of areas of the IC.

Integrated Circuit Thermal Throttling With Workload Adapted Thermal Sensor Maximum Temperature

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US Patent:
20170177044, Jun 22, 2017
Filed:
Dec 18, 2015
Appl. No.:
14/975356
Inventors:
- Santa Clara CA, US
Ameya Limaye - Chandler AZ, US
International Classification:
G06F 1/20
Abstract:
A method and apparatus for integrated circuit (IC) thermal throttling is described. In one embodiment, the apparatus comprises a plurality of thermal sensors, each of the plurality of thermal sensors being located in an area in the IC to record a die temperature at a location in its associated area; and a thermal controller coupled to the plurality of thermal sensors to perform thermal throttling of the IC to reduce the temperature of the IC in response to the die temperature recorded by any one temperature sensors of the plurality of thermal sensors being greater than an individual temperature threshold for said any one temperature sensor, the individual temperature threshold for each temperature sensor being based on a maximum temperature allowed for the area in the IC in which said each thermal sensor is located and power supplied to a plurality of areas of the IC.

Low Temperature/High Temperature Solder Hybrid Solder Interconnects

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US Patent:
20140151096, Jun 5, 2014
Filed:
Dec 4, 2012
Appl. No.:
13/693403
Inventors:
Hongjin Jiang - Chandler AZ, US
Patrick N. Stover - Chandler AZ, US
Arun Kumar C. Nallani - Chandler AZ, US
Rajen Sidhu - Chandler AZ, US
Ameya Limaye - Chandler AZ, US
International Classification:
H05K 1/11
H05K 3/34
H05K 1/09
US Classification:
174257, 174250, 29840
Abstract:
Embodiments of the present description relate to the field of fabricating microelectronic structures, wherein a microelectronic package may be attached to a microelectronic substrate with a hybrid solder interconnect. The hybrid solder interconnect may comprise a homogenous mixture of low temperature solder and a high temperature solder extending between at least one bond pad on a microelectronic package and at least one bond pad on a microelectronic substrate, wherein the relatively low reflow temperature used during the formation of the hybrid solder interconnect may prevent solder defects caused by warpage which may occur during the attachment of the microelectronic package to the microelectronic substrate.

Using Collapse Limiter Structures Between Elements To Reduce Solder Bump Bridging

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US Patent:
20140091456, Apr 3, 2014
Filed:
Sep 28, 2012
Appl. No.:
13/631713
Inventors:
Ameya LIMAYE - Chandler AZ, US
Richard J. HARRIES - Chandler AZ, US
Sandeep B. SANE - Chandler AZ, US
International Classification:
H01L 23/498
H01L 21/50
US Classification:
257737, 438125, 257E23068, 257E21499
Abstract:
Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface.Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.
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Ameya S Limaye from Portland, OR, age ~44 Get Report