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Alireza Kaviani

from Hayward, CA
Age ~83
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Also known as:
Helen O Fagan
Related to:
Sarah J Fagan, 42Christopher Paul Fagan, 47Michael A Fagan, 43Helen O FaganPamela F Fagan, 70Maryam KavianiWilliam J FaganMasoud Kaviani, 54
Connected to:
Ali Kaviani, 81Sara G Kaviar, 66Ingrid R Kavic, 39John A Kavic, 47Kalyan K Kavili, 42Hymie Kavin, 91Faranaz F Kavina, 55Paul A Kavinoky, 56George W Kavinsky, 55Jenny Kavinsky, 46

Alireza Kaviani Phones & Addresses

  • Hayward, CA

Resumes

Resumes

Alireza Kaviani Photo 1

Alireza Kaviani

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Alireza Kaviani Photo 2

Principal Engineer, Ph.d. ,Xilinx Inc.

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Position:
Principal Engineer at Xilinx
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Xilinx since Jun 1999
Principal Engineer
University of Toronto Jun 1998 - Jun 1999
Lecturer
Hewlett-Packard 1995 - 1997
Research Engineer
Overseas companies 1989 - 1991
Design Engineer
Education:
University of Toronto 1992 - 1998
M.A.Sc & Ph.D., Electrical and Computer Engineering Sharif University of Technology 1983 - 1989
B.Sc., Electrical Engineering (Electronics)
Skills:
Circuit Design
Clocking
FPGA
Xilinx
Integrated Circuit Design
Electrical Engineering
RTL design
ModelSim
Verilog
ASIC
PCIe
Hardware Architecture
VHDL
VLSI
SoC
Interests:
Volleyball, Soccer, Squash, Table tennis

Publications

Us Patents

Implementing Wide Multiplexers In An Fpga Using A Horizontal Chain Structure

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US Patent:
6466052, Oct 15, 2002
Filed:
May 15, 2001
Appl. No.:
09/858991
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19177
US Classification:
326 41, 326 38, 326 39, 326 40, 326 47
Abstract:
Methods and structures for implementing wide multiplexers in programmable logic devices (PLDs) in a distributed fashion. According to one embodiment, a configurable logic structure includes a function generator, a carry multiplexer, and an OR gate. The function generator is configured to implement a multiplexing function (under control of a first select signal) and an AND function (ANDing the output of the multiplexer with a second select signal). The carry multiplexer is configured to perform an AND function between an output of the function generator and a third select signal. Thus, with three select signals available, an 8-to-1 multiplexer can be implemented by combining the outputs of four different logic structures that use different values of the select signals. This combination of outputs is performed by forming an OR chain, with the OR input of each stage being provided by the associated carry multiplexer.

Configurable Logic Block For Pld

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US Patent:
6480023, Nov 12, 2002
Filed:
Oct 13, 2000
Appl. No.:
09/687812
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19173
US Classification:
326 38, 326 47
Abstract:
A method and apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice to output of another slice preceding the first slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions.

Fpga With Improved Structure For Implementing Large Multiplexers

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US Patent:
6556042, Apr 29, 2003
Filed:
Feb 20, 2002
Appl. No.:
10/080103
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19177
US Classification:
326 39, 326 47, 327407
Abstract:
Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Configurable Logic Block For Pld With Logic Gate For Combining Output With Another Configurable Logic Block

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US Patent:
6603332, Aug 5, 2003
Filed:
Nov 9, 2001
Appl. No.:
10/008556
Inventors:
Alireza S. Kaviani - San Jose CA
Sundararajarao Mohan - Sunnyvale CA
Ralph D. Wittig - Menlo Park CA
Steven P. Young - Boulder CO
Bernard J. New - Carmel Valley CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19177
US Classification:
326 39, 326 38, 326 41
Abstract:
An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

Literal Sharing Method For Fast Sum-Of-Products Logic

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US Patent:
6754686, Jun 22, 2004
Filed:
Oct 13, 2000
Appl. No.:
09/687868
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 738
US Classification:
708232, 326 39
Abstract:
A method and apparatus for implementing fast sum-of-products logic in a Field Programmable Gate Array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice to output of another slice preceding the first slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices.

Phase Detector Employing Asynchronous Level-Mode Sequential Circuitry

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US Patent:
6756822, Jun 29, 2004
Filed:
Oct 31, 2002
Appl. No.:
10/285037
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 900
US Classification:
327 3, 327 12
Abstract:
A phase detector employing asynchronous level-mode sequential circuitry is described. The phase detector includes edge detection circuitry for generating a first edge detection signal and a second edge detection signal. The first edge detection signal is indicative of an edge in a first clock signal, and the second edge detection signal is indicative of an edge in a second clock signal. The phase detector further includes a state machine that is asynchronously responsive to level changes in the first and second edge signals. The state machine generates a control signal indicative of which of the first and second clock signals is leading the other of the first and second clock signals.

Fpga With Improved Structure For Implementing Large Multiplexers

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US Patent:
6784692, Aug 31, 2004
Filed:
Feb 25, 2003
Appl. No.:
10/375791
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19177
US Classification:
326 39, 326 47, 327407
Abstract:
Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Method And Apparatus For Reducing Jitter In A Delay Line And A Trim Unit

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US Patent:
6788124, Sep 7, 2004
Filed:
Oct 31, 2002
Appl. No.:
10/285202
Inventors:
Alireza S. Kaviani - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 513
US Classification:
327276, 327281, 327261
Abstract:
A method and apparatus for reducing jitter in a delay line and trim unit is described. The trim unit includes a plurality of delay elements in parallel. At least one of the plurality of delay elements is controllable between on and off states. At least one of the plurality of delay elements includes at least one filter element to filter local supply noise. At least one of the plurality of delay elements includes a plurality of delay circuits having at least one gated delay circuit to control propagation of a clock signal through the plurality of delay circuits. The plurality of delay elements are configured to maintain an overall propagation delay without adding additional circuitry by sizing at least one delay circuit to provide longer propagation delay and sizing the other delay circuits to provide smaller propagation delay. The plurality of delay circuits are sized and arranged to minimize jitter.
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Alireza Kaviani from Hayward, CA, age ~83 Get Report